6.3.4 External ROM cycles
The following timing diagrams illustrate the external ROM cycles depending on the settings in the bus control
register and bus speed control register.
(1) Ordinary ROM read cycle
TClock
(internal)
ADD(21:0)
(output)
ROMCS(3:0)#
(output)
MEMRD#
(output)
DATA(15:0)
(read)
Remark A circle in the figure indicates the sampling timing.
CHAPTER 6 BUS CONTROL
Figure 6-3. Ordinary ROM Read Cycle (WROMA(3:0) = 0101)
User's Manual U14272EJ3V0UM
Valid
WROMA(3:0)
Valid
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