Gpintstat (0X0B00 0314) - NEC VR4181 mPD30181 User Manual

13.3.11 GPINTSTAT (0x0B00 0314)

Bit 15
Name GISTS15
R/W R/W
RTCRST 0
Note
Other resets
Bit 7
Name GISTS7
R/W R/W
RTCRST 0
Other resets Note
Bit Name
15 to 0 GISTS(15:0)
Note Holds the value before reset
Interrupt request pending status is reflected regardless of the setting of the interrupt mask bits. Therefore, the
status of an interrupt request can be returned as pending when this register is read even though the interrupt is
masked.
When a GPIO interrupt request is defined as an edge triggered type, the interrupt request is cleared by writing 1 to
the corresponding bit of this register. For example, if GPIO11 is defined as an edge triggered interrupt request input,
an interrupt request generated by this pin would be cleared by writing 1 to the bit 11 of this register.
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CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU)
14 13
GISTS14 GISTS13 GISTS12
R/W R/W
0 0
Note Note
6 5
GISTS6 GISTS5 GISTS4
R/W R/W
0 0
Note Note
GPIO interrupt request status. There is a one-to-one correspondence between
these bits and GPIO pins. When a GPIO pin is defined as a general-purpose
input, these bits reflect the interrupt request status as follows:
0 : No Interrupt request pending
1 : Interrupt request pending
User's Manual U14272EJ3V0UM
12 11
GISTS11 GISTS10
R/W R/W R/W
0 0
Note Note Note
4 3
GISTS3 GISTS2
R/W R/W R/W
0 0
Note Note Note
Function
10 9 8
GISTS9 GISTS8
R/W R/W
0 0 0
Note Note
2 1 0
GISTS1 GISTS0
R/W R/W
0 0 0
Note Note