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15.2.11 INTREG (0x0B00 017C)
Bit
15
Name
Reserved
R/W
R
RTCRST
0
Other resets
0
Bit
7
Name
Reserved
R/W
R
RTCRST
0
Other resets
0
Bit
Name
15 to 10
Reserved
9
MIDLEINTR
8
MSTINTR
7 to 2
Reserved
1
SIDLEINTR
0
Reserved
This register indicates occurrence of various interrupt request of the AIU.
When data is received from the A/D converter, the MIDLEINTR bit is set if valid data still exists in the MIDATREG
register (MIDATV bit = 1). In this case, the MIDATREG register is overwritten.
The MSTINTR bit is set when data is received in the MDMADATREG register.
When data is passed to the D/A converter, the SIDLEINTR bit is set if there is no valid data in the SODATREG
register (SODATV bit = 0). However, this interrupt request is valid only after AIUSEN bit = 1 in the SODATREG
register, after which SODATV bit = 1 in the DVALIDREG register.
CHAPTER 15 AUDIO INTERFACE UNIT (AIU)
14
13
Reserved
Reserved
Reserved
R
R
0
0
0
0
6
5
Reserved
Reserved
Reserved
R
R
0
0
0
0
0 is returned when read
Microphone idle interrupt request (receive data loss). Cleared to 0 when 1 is written.
1 : Occurred
0 : Normal
Microphone receive completion interrupt request. Cleared to 0 when 1 is written.
1 : Occurred
0 : Normal
0 is returned when read
Speaker idle interrupt request (mute). Cleared to 0 when 1 is written.
1 : Occurred
0 : Normal
0 is returned when read
User's Manual U14272EJ3V0UM
12
11
10
Reserved
Reserved
R
R
R
0
0
0
0
4
3
Reserved
Reserved
R
R
R
0
0
0
0
Function
9
8
MIDLEINTR
MSTINTR
R/W
R/W
0
0
0
0
0
0
2
1
0
SIDLEINTR
Reserved
R/W
R
0
0
0
0
0
0
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