Siums_2 (0X0C00 0006) - NEC VR4181 mPD30181 User Manual

20.3.11 SIUMS_2 (0x0C00 0006)

Bit 7
Name MSR7
R/W R
RTCRST Undefined
Other resets Undefined
Bit Name
7 MSR7
6 MSR6
5 MSR5
4 MSR4
3 MSR3
2 MSR2
1 MSR1
0 MSR0
This register indicates the current status and change in status of various control signals that are input to the CPU
from a modem or other peripheral device.
The MSR(3:0) bits are cleared to 0 if they are read when they are set to 1.
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CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2)
6 5
MSR6 MSR5
R R
Undefined Undefined Undefined
Undefined Undefined Undefined
DCD2# signal status
1 : Low level
0 : High level
RI signal (internal) status
1 : Low level
0 : High level
DSR2# input status
1 : Low level
0 : High level
CTS2# input status
1 : Low level
0 : High level
DCD2# signal change
1 : Changed
0 : No change
RI signal (internal) change
1 : Changed
0 : No change
DSR2# signal change
1 : Changed
0 : No change
CTS2# signal change
1 : Changed
0 : No change
User's Manual U14272EJ3V0UM
4 3
MSR4 MSR3 MSR2
R R/W
0
0
Function
2 1
MSR1 MSR0
R/W R/W R/W
0 0
0 0
0
0
0