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19.3.10 SIULS_1 (0x0C00 0015)
Bit
7
Name
LSR7
R/W
R
RTCRST
0
Other resets
0
Bit
Name
7
LSR7
6
LSR6
5
LSR5
4
LSR4
3
LSR3
2
LSR2
1
LSR1
0
LSR0
The CPU uses this register to get information related to data transfers.
When LSR7 and LSR(4:1) bits are 1, reading this register clears these bits to 0.
Caution The LSR0 bit (receive data ready bit) is set before the serial data reception is completed.
Therefore, the LSR0 bit may not be cleared if the serial receive data is read from the SIURB_1
register immediately after this bit is set.
When reading data from the SIURB_1 register, wait for the stop bit width time since the LSR0 bit
is set.
CHAPTER 19 SERIAL INTERFACE UNIT 1 (SIU1)
6
5
LSR6
LSR5
LSR4
R
R
1
1
1
1
Error detection (FIFO mode)
1 : Parity error, framing error, or break is detected.
0 : No error
Transmit block empty
1 : No data in transmit holding register and transmit shift register
No data in transmit FIFO (during FIFO mode)
0 : Data exists in transmit holding register or transmit shift register
Data exists in transmit FIFO (during FIFO mode)
Transmit holding register empty
1 : Character is transferred to transmit shift register (during 16450 mode)
Transmit FIFO is empty (during FIFO mode)
0 : Character is stored in transmit holding register (during 16450 mode)
Transmit data exists in transmit FIFO (during FIFO mode)
Break interrupt
1 : Detected
0 : No break
Framing error
1 : Detected
0 : No error
Parity error
1 : Detected
0 : No error
Overrun error
1 : Detected (receive data is overwritten)
0 : No error
Receive data ready
1 : Receive data exists in FIFO
0 : No receive data in FIFO
User's Manual U14272EJ3V0UM
4
3
2
LSR3
LSR2
R
R
R
0
0
0
0
0
0
Function
1
0
LSR1
LSR0
R
R
0
0
0
0
373
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