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Figure 10-1. Transition of V
Standby
mode
Transition No.
(1)
STANDBY instruction
(2)
All interrupt requests
(3)
SUSPEND instruction
<After transition> DRAM self refresh
(4)
Assertion of POWER
Assertion and then deassertion of RSTSW#
Interrupt request such as: ElapsedTime timer
(5)
HIBERNATE instruction
<After transition> DRAM self refresh
(6)
Assertion of POWER
Interrupt request such as: ElapsedTime timer
(7)
Assertion of RTCRST#
<After transition> Deassertion of MPOWER
(8)
Assertion and then deassertion of RTCRST#
BATTINH = high (normal activation)
(9)
Assertion and then deassertion of RTCRST#
BATTINH = low (BATTINH shutdown)
CHAPTER 10 POWER MANAGEMENT UNIT (PMU)
(2)
(1)
Fullspeed
mode
(6)
(5)
Hibernate
mode
RTCLong1
RTCLong2
Deassertion of MPOWER
DCD1#
User's Manual U14272EJ3V0UM
4181 Power Mode
R
Suspend
mode
(3)
(4)
(8)
RTC
reset
(9)
Factors
Key press
Pen touch
GPIO(15:0)
GPIO(15:0)
CF_BUSY#
(7)
DCD1# (SIU1)
CF_BUSY#
BATTINTR
189
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