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10.4 Shutdown Control
The operations of the RTC, peripheral units, and CPU core, and PMUINTREG register bit settings during a reset
are listed below.
For detail of the timing of each shutdown, refer to CHAPTER 5 INITIALIZATION INTERFACE.
Shutdown type
HALTimer shutdown
Software shutdown
BATTINH shutdown
10.4.1 HALTimer shutdown
After the CPU core is activated (following the mode change from Shutdown or Hibernate mode to Fullspeed
mode), or the CPU core is reset by RSTSW reset, software must write 1 to HALTIMERRST bit in the PMUCNTREG
register within about four seconds to clear the HALTimer.
If the HALTimer is not reset within about four seconds after the CPU core is activated or the RSTSW reset is
canceled, the PMU resets all peripheral units except for RTC and PMU. Then the PMU resets (Cold Reset) the CPU
core.
In addition, TIMOUTRST bit in PMUINTREG register is set to 1. After the CPU core is restarted, TIMOUTRST bit
must be checked and cleared to 0 by software.
10.4.2 Software shutdown
When the HIBERNATE instruction is executed, the PMU checks for currently pending interrupt requests. If there
are no pending interrupt requests, it stops the CPU core clock. It then resets all peripheral units except for the RTC,
GIU, and the PMU.
The PMU register contents do not change.
10.4.3 BATTINH shutdown
If the BATTINH signal is asserted when the CPU core is going to be activated, the PMU stops CPU activation and
resets all peripheral units except for the RTC, GIU, and the PMU. Then it resets the CPU core.
In addition, BATTINH bit in the PMUINTREG register is set to 1. After the CPU core is restarted, BATTINH bit
must be checked and cleared to 0 by software.
For details of the timing of BATTINH shutdown, see 10.5 Power-on Control below.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU)
Table 10-3. Operations During Shutdown
RTC, GIU
Peripheral units
Active
Reset
Active
Reset
Active
Reset
User's Manual U14272EJ3V0UM
CPU core
PMUINTREG bits
Cold Reset
TIMOUTRST = 1
Cold Reset
Cold Reset
BATTINH = 1
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