NEC VR4181 mPD30181 User Manual page 15

CHAPTER 5 INITIALIZATION INTERFACE ....................................................................................... 96
5.1 Reset Function ......................................................................................................................... 96
5.1.1 RTC reset ....................................................................................................................................
5.1.2 RSTSW reset ..............................................................................................................................
5.1.3 Deadman's Switch reset ..............................................................................................................
5.1.4 Software shutdown ...................................................................................................................... 100
5.1.5 HALTimer shutdown .................................................................................................................... 101
5.2 Power-on Sequence ................................................................................................................ 102
5.3 Reset of CPU Core ................................................................................................................... 104
5.3.1 Cold Reset ................................................................................................................................... 104
5.3.2 Soft Reset .................................................................................................................................... 105
5.4 Notes on Initialization ............................................................................................................. 106
5.4.1 CPU core ..................................................................................................................................... 106
5.4.2 Internal peripheral units ............................................................................................................... 106
5.4.3 Returning from power mode ........................................................................................................ 107
CHAPTER 6 BUS CONTROL .............................................................................................................. 108
6.1 MBA Host Bridge ..................................................................................................................... 108
6.1.1 MBA Host Bridge ROM and register address space ................................................................... 109
6.1.2 MBA modules address space ...................................................................................................... 109
6.2 Bus Control Registers ............................................................................................................. 110
6.2.1 BCUCNTREG1 (0x0A00 0000) ................................................................................................... 111
6.2.2 CMUCLKMSK (0x0A00 0004) ..................................................................................................... 112
6.2.3 BCUSPEEDREG (0x0A00 000C) ................................................................................................ 113
6.2.4 BCURFCNTREG (0x0A00 0010) ................................................................................................ 115
6.2.5 REVIDREG (0x0A00 0014) ......................................................................................................... 116
6.2.6 CLKSPEEDREG (0x0A00 0018) ................................................................................................. 117
6.3 ROM Interface .......................................................................................................................... 118
6.3.1 External ROM devices memory mapping .................................................................................... 118
6.3.2 Connection to external ROM (x 16) devices ................................................................................ 119
6.3.3 Example of ROM connection ....................................................................................................... 120
6.3.4 External ROM cycles ................................................................................................................... 125
6.4 DRAM Interface ........................................................................................................................ 128
6.4.1 EDO DRAM configuration ............................................................................................................ 128
6.4.2 Mixed memory mode (EDO DRAM only) ..................................................................................... 129
6.4.3 EDO DRAM timing parameters ................................................................................................... 129
6.4.4 SDRAM configuration .................................................................................................................. 130
6.5 Memory Controller Register Set ............................................................................................. 131
6.5.1 EDOMCYTREG (0x0A00 0300) .................................................................................................. 131
6.5.2 MEMCFG_REG (0x0A00 0304) .................................................................................................. 133
6.5.3 MODE_REG (0x0A00 0308) ....................................................................................................... 135
6.5.4 SDTIMINGREG (0x0A00 030C) .................................................................................................. 136
6.6 ISA Bridge ................................................................................................................................ 137
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