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10.5.3 Activation via GPIO activation interrupt request
When any of the GPIO(15:0) signals are asserted, the PMU checks the GPIO(15:0) activation interrupt enable bits
in the GIU. If GPIO(15:0) activation interrupts are enabled, the PMU asserts the POWERON signal to provide an
external notification that the CPU core is being activated (since the GPIO(15:0) activation enable interrupt bits are
cleared after an RTC reset, the GPIO(15:0) signal cannot be used for activation immediately after an RTC reset).
After asserting the POWERON signal, the PMU checks the BATTINH signal and de-asserts the POWERON
signal.
If the BATTINH signal is at high level, the PMU cancels the peripheral unit reset and starts the Cold Reset
sequence to activate the CPU core.
If the BATTINH signal is at low level, the PMU sets 1 to the BATTINH bit in the PMUINTREG register and then
performs another shutdown. After the CPU core is restarted, the BATTINH bit must be checked and cleared to 0 by
software.
The CPU core sets 1 to the GPWAKEUP bit in the PMUINTREG register regardless of whether activation
succeeds or fails.
Caution The changes in the GPIO signals are ignored while POWERON signal is active.
Figure 10-7. Activation via GPIO Activation Interrupt Request (BATTINH = H)
RTC (Internal)
GPIO (15:0) (I/O)
POWERON (Output)
MPOWER (Output)
BATTINH/BATTINT# (Input)
Figure 10-8. Activation via GPIO Activation Interrupt Request (BATTINH = L)
RTC (Internal)
GPIO (15:0) (I/O)
POWERON (Output)
MPOWER (Output)
BATTINH/BATTINT# (Input)
CHAPTER 10 POWER MANAGEMENT UNIT (PMU)
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User's Manual U14272EJ3V0UM
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