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Bit
Name
5 to 3
Reserved
2, 1
B0Config(1:0)
0
EDO/SDRAM
This register is used to set DRAM type (capacity, type, organization, etc.) of Bank 0 and Bank 1.
Caution When using SDRAMs, set the Init bit to 1 to initialize SDRAMs before accessing them after an
RTC reset or RSTSW reset is canceled or after the V
initialization of SDRAMs must be executed until the V
cycle.
Remark
During the 64 Mbit SDRAM mode register write, A13 of the address bus is at high level. On the other
hand, during the 16 Mbit SDRAM mode register write, A13 is at low level. In order to initialize 64-Mbit
SDRAM correctly, software must execute the following sequence.
<1> Set B0Config(1:0) and B1Config(1:0) bits of MEMCFG_REG register to 01
<2> Set MODE_REG register to appropriate value (0x00n7, n can be any value)
<3> Initialize SDRAM by setting Init bit of MEMCFG_REG register
<4> Set B0Config(1:0) and B1Config(1:0) bits of MEMCFG_REG register to 10
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CHAPTER 6 BUS CONTROL
0 is returned when read
Bank 0 Capacity
00 : Bank 0 is not installed
01 : 16 Mbit
10 : 64 Mbit
11 : Reserved
DRAM Type
0 : EDO DRAM
1 : SDRAM
R
User's Manual U14272EJ3V0UM
Function
4181 restores from the Hibernate mode. An
4181 issues the first CBR auto refresh
R
(2/2)
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