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19.3.6 SIUIID_1 (0x0C00 0012: Read)
Bit
7
Name
IIR7
R/W
R
RTCRST
0
Other resets
0
Bit
Name
7, 6
IIR(7:6)
5, 4
Reserved
3
IIR3
2, 1
IIR(2:1)
0
IIR0
This register indicates priority levels for interrupts and existence of pending interrupt requests.
From highest to lowest priority, the involved interrupts are the receive line status, the receive data ready, the
character timeout, the transmit holding register empty, and the modem status.
The content of the IIR3 bit is valid only in the FIFO mode and it is always 0 in the 16450 mode.
The IIR2 bit becomes 1 when the IIR3 bit is set to 1.
366
CHAPTER 19 SERIAL INTERFACE UNIT 1 (SIU1)
6
5
IIR6
Reserved
Reserved
R
R
0
0
0
0
Becomes 11 when FCR0 bit = 1
0 is returned when read
Pending of the character timeout interrupt request (in FIFO mode)
1 : No pending
0 : Pending
Indicates the priority level of interrupts.
See the following table.
Pending interrupt requests
1 : No pending
0 : Pending
User's Manual U14272EJ3V0UM
4
3
2
IIR3
IIR2
R
R
R
0
0
0
0
0
0
Function
1
0
IIR1
IIR0
R
R
0
1
0
1
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