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5.1.4 Software shutdown
When the software executes the HIBERNATE instruction, the V
enters reset status. Recovery from reset status occurs when the POWER pin or DCD# signal is asserted or when an
unmasked wake-up interrupt request is occurred.
A reset by software shutdown initializes the entire internal state except for the RTC timer, the GIU, and the PMU.
After a reset, the processor becomes the system bus master, which executes a Cold Reset exception sequence
and begins to access the reset vectors in the ROM space. Since only part of the internal status is reset when a reset
occurs in the V
4181, the processor should be completely initialized by software (see 5.4 Notes on Initialization).
R
Cauiton The V
4181 does not set the DRAM to self-refresh mode at the transition to Hibernate mode from
R
Fullspeed mode. To preserve DRAM data, software must set the DRAM to self-refresh mode. For
details, refer to CHAPTER 10 POWER MANAGEMENT UNIT (PMU).
POWER (Input)
POWERON (Output)
MPOW ER (Output)
ColdReset# (Internal)
Reset# (Internal)
PLL (Internal)
RTC (Internal,
32.768 kHz)
Notes 1. Wait time for activation. It can be changed by setting the PMUWAITREG register.
2. MasterClock is the basic clock used in the CPU core.
frequency.
100
CHAPTER 5 INITIALIZATION INTERFACE
Figure 5-4. Software Shutdown
Stable oscillation
> 32 ms
User's Manual U14272EJ3V0UM
4181 sets the MPOWER pin as inactive, then
R
Stopped
Undefined
Note1
Its frequency is one forth of TClock
Stable oscillation
16 ms
Note2
16MasterClock
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