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CHAPTER 21 LCD CONTROLLER
(2) Load clock
The edge positions of the load clock, LOCLK, are programmable. Each row in the rectangle specified with (0, 0)
and (Htotal–1, Vvisible–1) must have two LOCLK edges. The remaining rows in the frame rectangle form the
vertical blank. These rows also have two LOCLK edges if the DummyL bit of the VRVISIBREG register is 1, or
none if DummyL bit is 0. The first LOCLK edge is defined by the LCS(7:0) bits of the LDCLKSTREG register. The
second edge is defined by the LCE(7:0) bits of the LDCLKENDREG register, and is usually inside the horizontal
blank.
The LPPOL bit of the LCDCTRLREG register controls the directions of toggles. If the LPPOL bit is 0, the first
LOCLK edge is positive and the second is negative. If the LPPOL bit is 1, the reverse is true.
Figure 21-3. Position of Load Clock (LOCLK)
Origin
(Hvisible−1, 0)
(Htotal−1, 0)
(0, 0)
X
View rectangle
Horizontal blank
(0, Vvisible−1)
Vertical blank
(0, Vtotal−1)
Y
(X = LCE x 2)
(X = LCS x 2)
LOCLK
1st edge
2nd edge
Caution The following expression must be satisfied.
1. Htotal > LCE(7:0) x 2 > LCS(7:0) x 2
403
User's Manual U14272EJ3V0UM
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