Chapter 7 Dma Control Unit (Dcu); General - NEC VR4181 mPD30181 User Manual

64-/32-bit microprocessor hardware
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7.1 General

The DMA Control Unit (DCU) controls four channels of DMA transfer. Two of them are allocated for the AIU
(microphone and speaker), though the remaining two are reserved for future use.
The Microphone channel performs the I/O-to-memory transfers from the A/D converter included in the AIU to
memory. The Speaker channel performs the memory-to-I/O transfers from memory to the D/A converter included in
the AIU.
Each DMA channel supports both the primary and the secondary memory buffers. The Source1/Source2 or
Destination1/Destination2 Address registers for the associated channel determine the starting address of each
memory buffer. The sizes of memory buffers are determined in the associated record length registers.
The DCU uses the primary and secondary DMA buffers alternately when transferring. For example, during the first
DMA transfer following either hardware or software reset of the DCU, the transfer starts using the primary DMA
buffer. If the total number of DMA transfers through the primary DMA buffer reaches the value set in the associated
record length register, the next DMA transfer is performed using the secondary DMA buffer. Software must keep track
of which buffer contains valid DMA data.
Software may configure any of the DMA channels to operate in one of two modes; auto-stop or auto-load. When a
channel is configured to operate in auto-stop mode, the DCU terminates DMA transfers after the number of transfers
specified by the record length register and automatically resets the DMA mask bit for that channel. Once the mask bit
is automatically reset, the DCU ignores all subsequent DMA requests for this channel. To resume DMA transfers in
this mode, software must again unmask DMA transfers for this channel. Once software unmasks DMA requests, the
DCU resumes DMA transfers utilizing the secondary memory buffer.
When a channel is configured to operate in auto-load mode, the DCU does not terminate DMA transfers after the
number of DMA transfers specified by the record length register. Instead, the DCU automatically switchs to the
secondary DMA buffer and continues servicing DMA requests.
In either mode, auto-stop or auto-load, the DCU always alternates the DMA buffer to be used between the primary
and secondary buffers. Software must keep track of the total number of transfers and assure the appropriate DMA
buffer is loaded with new DMA data before starting another DMA transfer.
The DCU can be programmed to generate an EOP (end of process) interrupt request independent of auto-stop or
auto-load mode. An EOP interrupt request is generated once the number of DMA transfers has reached to the value
specified by the record length register.
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CHAPTER 7 DMA CONTROL UNIT (DCU)

User's Manual U14272EJ3V0UM

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