NEC VR4181 mPD30181 User Manual page 17

9.2.4 SOFTINTREG (0x0A00 009A) .................................................................................................... 179
9.2.5 SYSINT2REG (0x0A00 0200) ..................................................................................................... 180
9.2.6 MSYSINT2REG (0x0A00 0206) .................................................................................................. 181
9.2.7 PIUINTREG (0x0B00 0082) ........................................................................................................ 182
9.2.8 AIUINTREG (0x0B00 0084) ........................................................................................................ 183
9.2.9 KIUINTREG (0x0B00 0086) ........................................................................................................ 184
9.2.10 MPIUINTREG (0x0B00 008E) ................................................................................................... 185
9.2.11 MAIUINTREG (0x0B00 0090) ................................................................................................... 186
9.2.12 MKIUINTREG (0x0B00 0092) ................................................................................................... 187
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) ...................................................................... 188
10.1 General ................................................................................................................................... 188
10.2 V 4181 Power Mode .............................................................................................................. 188
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10.2.1 Power mode and state transition ............................................................................................... 188
10.3 Reset Control ......................................................................................................................... 191
10.3.1 RTC reset .................................................................................................................................. 191
10.3.2 RSTSW reset ............................................................................................................................ 192
10.3.3 Deadman's Switch reset ............................................................................................................ 192
10.3.4 Preserving DRAM data on RSTSW reset .................................................................................. 192
10.4 Shutdown Control ................................................................................................................. 193
10.4.1 HALTimer shutdown .................................................................................................................. 193
10.4.2 Software shutdown .................................................................................................................... 193
10.4.3 BATTINH shutdown ................................................................................................................... 193
10.5 Power-on Control ................................................................................................................... 194
10.5.1 Activation via Power Switch interrupt request ........................................................................... 195
10.5.2 Activation via CompactFlash interrupt request .......................................................................... 196
10.5.3 Activation via GPIO activation interrupt request ........................................................................ 197
10.5.4 Activation via DCD interrupt request ......................................................................................... 198
10.5.5 Activation via ElapsedTime (RTC alarm) interrupt request ....................................................... 200
10.6 DRAM Interface Control ........................................................................................................ 201
10.6.1 Entering Hibernate mode (EDO DRAM) .................................................................................... 201
10.6.2 Entering Hibernate mode (SDRAM) .......................................................................................... 202
10.6.3 Exiting Hibernate mode (EDO DRAM) ...................................................................................... 203
10.6.4 Exiting Hibernate mode (SDRAM) ............................................................................................. 204
10.6.5 Entering Suspend mode (EDO DRAM) ..................................................................................... 205
10.6.6 Entering Suspend mode (SDRAM) ............................................................................................ 206
10.6.7 Exiting Suspend mode (EDO DRAM) ........................................................................................ 207
10.6.8 Exiting Suspend mode (SDRAM) .............................................................................................. 207
10.7 Register Set ............................................................................................................................ 208
10.7.1 PMUINTREG (0x0B00 00A0) .................................................................................................... 209
10.7.2 PMUCNTREG (0x0B00 00A2) .................................................................................................. 211
10.7.3 PMUWAITREG (0x0B00 00A8) ................................................................................................. 213
10.7.4 PMUDIVREG (0x0B00 00AC) ................................................................................................... 214
10.7.5 DRAMHIBCTL (0x0B00 00B2) .................................................................................................. 215
User's Manual U14272EJ3V0UM
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