Table of Contents
Advertisement
The four modes of SCK are described below.
(1) When CKMD bit = 0 and CKPOL bit = 0
• Transmission
The first transmit data bit is output before the first rising edge of SCK.
The second transmit data and those that follow are output synchronized with the falling edge of SCK.
Therefore, the external master must sample the data synchronizing with the rising edge of SCK.
• Reception
The external master must output the first data bit before the first rising edge of SCK.
The V
4181 samples receive data synchronizing with the rising edge of SCK. Therefore, the external master
R
must output data synchronizing with the falling edge of SCK.
(2) When CKMD bit = 0 and CKPOL bit = 1
• Transmission
The first transmit data bit is output before the first falling edge of SCK.
The second transmit data bit and those that follow are output synchronized with the rising edge of SCK.
Therefore, the external master must sample the data synchronizing with the falling edge of SCK.
• Reception
The external master must output the first data bit before the first falling edge of SCK.
The V
4181 samples receive data synchronizing with the falling edge of SCK. Therefore, the external master
R
must output data synchronizing with the rising edge of SCK.
(3) When CKMD bit = 1 and CKPOL bit = 0
• Transmission
The first transmit data bit is output synchronized with the first rising edge of SCK.
The second transmit data bit and those that follow are output synchronized with the rising edge of SCK.
Therefore, the external master must sample the data synchronizing with the falling edge of SCK.
• Reception
The V
4181 samples receive data synchronizing with the falling edge of SCK. Therefore, the external master
R
must output data synchronizing with the rising edge of SCK.
(4) When CKMD bit = 1 and CKPOL bit = 1
• Transmission
The first transmit data bit is output synchronized with the first falling edge of SCK.
The second transmit data bit and those that follow are output synchronized with the falling edge of SCK.
Therefore, the external master must sample the data synchronizing with the rising edge of SCK.
• Reception
The V
4181 samples receive data synchronizing with the rising edge of SCK. Therefore, the external master
R
must output data synchronizing with the falling edge of SCK.
158
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI)
User's Manual U14272EJ3V0UM
Advertisement
Table of Contents
