Lcdctrlreg (0X0A00 0410) - NEC VR4181 mPD30181 User Manual

21.4.9 LCDCTRLREG (0x0A00 0410)

Bit 15
Name Reserved
R/W R
Reset 0
Bit 7
Name FIFOC2
R/W R/W
Reset 0
Bit Name
15 to 8 Reserved
7 to 5 FIFOC(2:0)
4 Reserved
3 ContCkE
2 LPPOL
1 FLMPOL
0 SCLKPOL
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CHAPTER 21 LCD CONTROLLER
14 13
Reserved Reserved Reserved
R R
0 0
6 5
FIFOC1 FIFOC0 Reserved
R/W R/W
0 0
0 is returned when read
FIFO control. A FIFO transfer is performed when only the number of double words
set here is left in the FIFO.
0 is returned when read
LCD controller clock enable
0 : OFF
1 : ON
LOCLK clock polarity
0 : Leading edge is rising
1 : Leading edge is falling
FLM clock polarity
0 : Leading edge is rising
1 : Leading edge is falling
Shift clock polarity
0 : Leading edge is rising (active edge is falling)
1 : Leading edge is falling (active edge is rising)
User's Manual U14272EJ3V0UM
12 11 10
Reserved Reserved
R R R
0 0
4 3
ContCkE LPPOL
R R/W R/W
0 0
Function
9 8
Reserved Reserved
R R
0 0 0
2 1 0
FLMPOL SCLKPOL
R/W R/W
0 0 0