Lcdcfgreg1 (0X0A00 0416) - NEC VR4181 mPD30181 User Manual

21.4.12 LCDCFGREG1 (0x0A00 0416)

Bit 15
Name Reserved
R/W R
Reset 0
Bit 7
Name Reserved
R/W R
Reset 0
Bit Name
15, 14 Reserved
13 to 8 HpckL(5:0)
7, 6 Reserved
5 to 0 HpckH(5:0)
CHAPTER 21 LCD CONTROLLER
14 13
Reserved HpckL5
R R/W
0 0
6 5
Reserved HpckH5
R R/W
0 0
0 is returned when read
Number of gclk cycles for hpck low level width
0 is returned when read
Number of gclk cycles for hpck high level width
User's Manual U14272EJ3V0UM
12 11
HpckL4 HpckL3 HpckL2
R/W R/W
0 0
4 3
HpckH4 HpckH3 HpckH2
R/W R/W
0 0
Function
10 9
HpckL1 HpckL0
R/W R/W R/W
0 0
2 1
HpckH1 HpckH0
R/W R/W R/W
0 0
8
0
0
0
421