NEC VR4181 mPD30181 User Manual page 19

13.3.12 GPHIBSTH (0x0B00 0316) ...................................................................................................... 263
13.3.13 GPHIBSTL (0x0B00 0318) ...................................................................................................... 264
13.3.14 GPSICTL (0x0B00 031A) ........................................................................................................ 265
13.3.15 KEYEN (0x0B00 031C) ........................................................................................................... 267
13.3.16 PCS0STRA (0x0B00 0320) ..................................................................................................... 268
13.3.17 PCS0STPA (0x0B00 0322) ..................................................................................................... 268
13.3.18 PCS0HIA (0x0B00 0324) ........................................................................................................ 269
13.3.19 PCS1STRA (0x0B00 0326) ..................................................................................................... 270
13.3.20 PCS1STPA (0x0B00 0328) ..................................................................................................... 270
13.3.21 PCS1HIA (0x0B00 032A) ........................................................................................................ 271
13.3.22 PCSMODE (0x0B00 032C) ..................................................................................................... 272
13.3.23 LCDGPMODE (0x0B00 032E) ................................................................................................ 273
13.3.24 MISCREGn (0x0B00 0330 to 0x0B00 034E) ........................................................................... 274
CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) ................................................................. 275
14.1 General ................................................................................................................................... 275
14.1.1 Block diagrams .......................................................................................................................... 276
14.2 Scan Sequencer State Transition ......................................................................................... 278
14.3 Register Set ............................................................................................................................ 280
14.3.1 PIUCNTREG (0x0B00 0122) ..................................................................................................... 281
14.3.2 PIUINTREG (0x0B00 0124) ...................................................................................................... 284
14.3.3 PIUSIVLREG (0x0B00 0126) .................................................................................................... 285
14.3.4 PIUSTBLREG (0x0B00 0128) ................................................................................................... 286
14.3.5 PIUCMDREG (0x0B00 012A) .................................................................................................... 287
14.3.6 PIUASCNREG (0x0B00 0130) .................................................................................................. 289
14.3.7 PIUAMSKREG (0x0B00 0132) .................................................................................................. 291
14.3.8 PIUCIVLREG (0x0B00 013E) .................................................................................................... 292
14.3.9 PIUPBnmREG (0x0B00 02A0 to 0x0B00 02AE, 0x0B00 02BC to 0x0B00 02BE) .................... 293
14.3.10 PIUABnREG (0x0B00 02B0 to 0x0B00 02B6) ........................................................................ 294
14.4 State Transition Flow ............................................................................................................ 295
14.5 Relationships among TPX, TPY, ADIN, and AUDIOIN Pins and States ............................ 297
14.6 Timing ..................................................................................................................................... 298
14.6.1 Touch/release detection timing ................................................................................................. 298
14.6.2 A/D port scan timing .................................................................................................................. 298
14.7 Data Loss Conditions ............................................................................................................ 299
CHAPTER 15 AUDIO INTERFACE UNIT (AIU) ................................................................................ 301
15.1 General ................................................................................................................................... 301
15.2 Register Set ............................................................................................................................ 302
15.2.1 SDMADATREG (0x0B00 0160) ................................................................................................. 303
15.2.2 MDMADATREG (0x0B00 0162) ................................................................................................ 304
15.2.3 DAVREF_SETUP (0x0B00 0164) ............................................................................................. 305
15.2.4 SODATREG (0x0B00 0166) ...................................................................................................... 306
15.2.5 SCNTREG (0x0B00 0168) ........................................................................................................ 307
15.2.6 SCNVC_END (0x0B00 016E) ................................................................................................... 308
15.2.7 MIDATREG (0x0B00 0170) ....................................................................................................... 309
User's Manual U14272EJ3V0UM
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