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Table No.
1-1.
Supported PClock and TClock Frequencies ............................................................................................... 31
1-2.
Devices Supported by System Bus ............................................................................................................. 31
1-3.
GPIO(31:0) Pin Functions ........................................................................................................................... 33
1-4.
LCD Panel Resolutions (in Pixels, TYP.) .................................................................................................... 34
1-5.
Functions of LCD Interface Pins when LCD Controller Is Disabled ............................................................ 34
1-6.
System Control Coprocessor (CP0) Register Definitions ........................................................................... 43
1-7.
List of Instructions Supported by V
3-1.
CP0 Registers ............................................................................................................................................. 68
3-2.
Cache Algorithm ......................................................................................................................................... 71
3-3.
Mask Values and Page Sizes ..................................................................................................................... 72
3-4.
Cause Register Exception Code Field ........................................................................................................ 80
4-1.
V
4181 Physical Address Space ................................................................................................................ 93
R
4-2.
ROM Address Map ..................................................................................................................................... 93
4-3.
Internal I/O Space 1 .................................................................................................................................... 94
4-4.
Internal I/O Space 2 .................................................................................................................................... 94
4-5.
MBA Bus I/O Space .................................................................................................................................... 95
4-6.
DRAM Address Map ................................................................................................................................... 95
6-1.
Bus Control Registers ................................................................................................................................. 110
6-2.
V
4181 EDO DRAM Capacity ..................................................................................................................... 129
R
6-3.
Memory Controller Registers ...................................................................................................................... 131
6-4.
ISA Bridge Registers ................................................................................................................................... 137
7-1.
DCU Registers ............................................................................................................................................ 144
8-1.
CSI Registers .............................................................................................................................................. 160
9-1.
ICU Registers .............................................................................................................................................. 173
10-1.
Overview of Power Modes .......................................................................................................................... 190
10-2.
Operations During Reset ............................................................................................................................ 191
10-3.
Operations During Shutdown ...................................................................................................................... 193
10-4.
PMU Registers ............................................................................................................................................ 208
11-1.
RTC Registers ............................................................................................................................................ 216
12-1.
DSU Registers ............................................................................................................................................ 230
13-1.
Alternate Functions of GPIO(15:0) Pins ...................................................................................................... 236
13-2.
Alternate Functions of GPIO(31:16) Pins .................................................................................................... 237
13-3.
CSI Interface Signals .................................................................................................................................. 238
13-4.
Serial Interface Channel 1 (SIU1) Signals .................................................................................................. 239
LIST OF TABLES (1/2)
Title
Series Processors ............................................................................. 46
R
User's Manual U14272EJ3V0UM
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