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3.2.17 WatchLo (18) and WatchHi (19) registers
The V
4181 processor provides a debugging feature to detect references to a selected physical address; load and
R
store instructions to the location specified by the WatchLo and WatchHi registers cause a Watch exception.
The contents of these registers are undefined after a reset so that they must be initialized by software.
31
PAddr0:
Specifies physical address bits 31 to 3.
Specifies detection of watch address references when load instructions are executed (1 → Detect,
R:
0 → Not detect).
Specifies detection of watch address references when store instructions are executed (1 → Detect,
W:
0 → Not detect).
0:
Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
31
0:
Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
CHAPTER 3 CP0 REGISTERS
Figure 3-20. WatchLo Register
PAddr0
Figure 3-21. WatchHi Register
0
User's Manual U14272EJ3V0UM
3
2
1
0
0
R
W
0
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