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32
memory
controller
MGCLK
MBAGP
interface
MGCLK
FIFOs
MBA
32
slave
interface
MBA clock
The LCD controller is a slave module of the MBA bus. Its registers can be accessed via the MBA slave interface.
The frame data are read from main memory via the memory controller and the MBAGP (MBA Graphic port).
CHAPTER 21 LCD CONTROLLER
Figure 21-1. LCD Controller Block Diagram
MBA
16
Bus
interface
unit
32
32
LCD
registers
Shift clock
Load clock
Timing
generator
FLM
LCD
interrupt request
User's Manual U14272EJ3V0UM
16
RAM
6R
6G
Color
Pixel
lookup
modulation
6B
18
256 x 18
palette
Data
(4 bits)
Data (4 bits)
Shift clock
GPU
Load clock
FLM
LCD Controller
1R
1G
Pixel
packing
1B
Data
(8 bits)
Data
(4 bits)
I/O
pins
401
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