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1.3.15 Programmable chip selects
The V
4181 provides support for 2 programmable chip selects (PCS) which are also available as general-purpose
R
I/O pins. Each PCS can decode either I/O or memory accesses and can optionally be qualified to read, write, or both
read and write.
1.3.16 LCD interface
The LCD controller of the V
system DRAM. The LCD controller supports monochrome STN LCD panels having 4-bit data bus interfaces and color
STN LCD panels having 8-bit data bus interface. When interfacing to a color LCD panel, general-purpose I/O pins
must be allocated to provide the upper nibble of the 8-bit LCD data bus.
In monochrome mode, the LCD controller supports 1-bpp mode (mono), 2-bpp mode (4 gray levels) and 4-bpp
mode (16 gray levels). In color mode, it supports 4-bpp mode (16 colors) and 8-bpp mode (256 colors).
The LCD controller includes a 256-entry x 18-bit color pallet. In 8-bpp color modes, the pallet is used to select 256
colors out of possible 262,144 colors.
The LCD controller supports LCD panels of up to 320 x 320 pixels. Typical LCD panel horizontal/vertical
resolutions are as follows.
The LCD controller also provides power-on and power-down sequence control for the LCD panel via the VPLCD
and VPBIAS pins. Power sequencing is provided to prevent latch-up damage to the panel.
The LCD controller can be disabled to allow connection of an external LCDC with integrated frame buffer RAM
such as NEC Electronics' µ PD16661. When the internal LCD controller is disabled, the SHCLK, LOCLK, VPLCD,
and VPBIAS pins are redefined as follows:
Table 1-5. Functions of LCD Interface Pins when LCD Controller Is Disabled
34
CHAPTER 1 INTRODUCTION
4181 is Unified Memory Architecture (UMA) based in which the frame buffer is part of
R
Table 1-4. LCD Panel Resolutions (in Pixels, TYP.)
Horizontal resolution
320
320
320
240
240
240
160
160
160
Redefined function
LCDCS#
MEMCS16#
VPGPIO1
VPGPIO0
User's Manual U14272EJ3V0UM
Vertical resolution
320
240
160
320
240
160
320
240
160
Default function
SHCLK
LOCLK
VPLCD
VPBIAS
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