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4.2 NMI Signal
The input signal (NMI signal) from the target system is delayed (t
FPGA before it is input to the I/O chip of the emulator.
In addition, the DC characteristics change. The input voltage becomes V
The input current becomes I
Target system
4.3 V
Signal
PP
The V
signal from the target system is connected to LED via a 330-Ω resistor in the emulator. It is not
PP
connected to the evaluation chip in the emulator.
Target system
4.4 MAM Register
Debugging of MAM register cannot be performed in the emulator. If debugging MAM register with software,
proceed with care.
In the target device, the port can be used as an address bus by setting a value to the MAM register (address:
FFFFF068H) that is mapped in the internal peripheral I/O area with the software (Separate bus function). In the
emulator, however, switching to the separate bus through MAM register setting by software is impossible.
To use the separate bus function, set the J1 jumper in advance. (refer to 2.5 Separate Bus Function Setting)
28
CHAPTER 4
= ±1.0 µ A (MAX.).
IN
Figure 4-2. NMI Signal Flow Path
NMI signal
NMI pin
Figure 4-3. V
V
signal
PP
330 Ω
CAUTIONS
= 10 ns (MAX.)) because it passes through
pD
= 2.0 V (MIN.) and V
IH
IE-703017-MC-EM1
FPGA
Signal Flow Path
PP
IE-703017-MC-EM1
LED
= 0.8 V (MAX.).
IL
I/O chip
Evaluation chip
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