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1.3.17 Wake-up events
The V
4181 supports 4 power management modes: Fullspeed, Standby, Suspend, and Hibernate. Of these
R
modes, Hibernate is the lowest power mode and results in the powering off of all system components including the
2.5 V logic in the V
4181. The V
R
powered during the Hibernate mode, as does the system DRAM. Software can configure the V
the Hibernate mode and returning to Fullspeed mode due to any one of the following events:
• Activation of the DCD1# pin
• Activation of the POWER pin
• RTC alarm
• Activation of one of the GPIO(15:0) pins
• Activation of the CF_BUSY# pin (CompactFlash interrupt request (IREQ))
Remark
Different from the V
wake-up events.
1.4 V
4110 CPU Core
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Figure 1-2 shows the internal block diagram of the V
In addition to the conventional high-performance integer operation units, this CPU core has the full-associative
format translation lookaside buffer (TLB), which has 32 entries that provide mapping to 2-page pairs (odd and even)
for one entry. Moreover, it also includes instruction cache, data cache, and bus interface.
Control(o)
Control(i)
Address/Data(o)
Address/Data(i)
Internal clock
CHAPTER 1 INTRODUCTION
4181 3.3 V logic, which includes RTC, PMU, and non-volatile registers, remain
R
TM
4111
or the V
4121
R
R
4110 CPU core.
R
Figure 1-2. V
4110 CPU Core Internal Block Diagram
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Virtual address bus
Internal data bus
Bus
Data
interface
cache
(4 KB)
User's Manual U14272EJ3V0UM
TM
, the V
4181 will wake up after RTC reset without these
R
Instruction
cache
(4 KB)
Clock
generator
4181 waking up from
R
CP0
CPU
TLB
35
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