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(1) Interrupt enable
Interrupts are enabled when all of the following conditions are true:
• IE bit is set to 1.
• EXL bit is cleared to 0.
• ERL bit is cleared to 0.
• The appropriate bit of the IM field is set to 1.
(2) Operating modes
The following Status register bit settings are required for User, Kernel, and Supervisor modes.
• The processor is in User mode when KSU = 10, EXL = 0, and ERL = 0.
• The processor is in Supervisor mode when KSU = 01, EXL = 0, and ERL = 0.
• The processor is in Kernel mode when KSU = 00, EXL = 1, or ERL = 1.
Access to the kernel address space is allowed when the processor is in Kernel mode.
Access to the supervisor address space is allowed when the processor is in Supervisor or Kernel mode.
Access to the user address space is allowed in any of the three operating modes.
(3) Addressing modes
The following Status register bit settings select 32- or 64-bit operation for each of User, Kernel, and Supervisor
operating modes. Enabling 64-bit operation permits the execution of 64-bit opcodes and translation of 64-bit
addresses. 64-bit operation for User, Kernel and Supervisor modes can be set independently.
• 64-bit addressing for Kernel mode is enabled when KX bit = 1. 64-bit operations are always valid in Kernel
mode. If this bit is set, an XTLB Refill exception occurs if a TLB miss occurs in the Kernel mode address
space.
• 64-bit addressing and operations are enabled for Supervisor mode when SX bit = 1. If this bit is set, an
XTLB Refill exception occurs if a TLB miss occurs in the Supervisor mode address space.
• 64-bit addressing and operations are enabled for User mode when UX bit = 1. If this bit is set, an XTLB Refill
exception occurs if a TLB miss occurs in the User mode address space.
(4) Status after reset
The contents of the Status register are undefined after Cold Resets, except for the following bits in the Diagnostic
Status field.
• TS and SR bits are cleared to 0.
SR bit is 0 after Cold Reset, and is 1 after Soft Reset or NMI.
• ERL and BEV bits are set to 1.
Remark
Cold Reset and Soft Reset are resets for the CPU core (see 5.3 Reset of CPU Core). For the
reset of all the V
INTERFACE and CHAPTER 10 POWER MANAGEMENT UNIT (PMU).
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CHAPTER 3 CP0 REGISTERS
4181 including peripheral units, refer to CHAPTER 5
R
User's Manual U14272EJ3V0UM
INITIALIZATION
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