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Bit
Name
5
TIMOUTRST
4
RTCRST
3
RSTSW
2
DMSRST
1
BATTINTR
0
POWERSWINTR
This register indicates the statuses of power-on factors and interrupt requests. It also indicates the status of the
DCD1# pin.
The BATTINTR bit is set to 1 when the BATTINH/BATTINT# signal becomes low and a battery-low interrupt
request occurs during modes other than the Hibernate mode (MPOWER = H).
The POWERSWINTR bit is set to 1 when the POWER signal becomes high and a Power Switch interrupt request
occurs during modes other than the Hibernate mode. However, this bit is not set to 1 when the POWER signal
becomes high during the Hibernate mode (MPOWER = L).
210
CHAPTER 10 POWER MANAGEMENT UNIT (PMU)
HALTimer reset request detection. Cleared to 0 when 1 is written.
1 : Detected
0 : Not detected
This bit must be checked and cleared to 0 after the CPU core is restarted.
RTC reset detection. Cleared to 0 when 1 is written.
1 : Detected
0 : Not detected
This bit must be checked and cleared to 0 after the CPU core is restarted.
RSTSW interrupt request detection. Cleared to 0 when 1 is written.
1 : Detected
0 : Not detected
This bit must be checked and cleared to 0 after the CPU core is restarted.
Deadman's Switch interrupt request detection. Cleared to 0 when 1 is written.
1 : Detected
0 : Not detected
This bit must be checked and cleared to 0 after the CPU core is restarted.
Battery low detection during normal operation. Cleared to 0 when 1 is written.
1 : Detected
0 : Not detected
This bit must be checked and cleared to 0 after the CPU core is restarted.
Power Switch interrupt request detection. Cleared to 0 when 1 is written.
1 : Detected
0 : Not detected
This bit must be checked and cleared to 0 after the CPU core is restarted.
User's Manual U14272EJ3V0UM
Function
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