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Physical address
0xFFFF FFFF to 0x2000 0000
0x1FFF FFFF to 0x1800 0000
0x17FF FFFF to 0x1400 0000
0x13FF FFFF to 0x1000 0000
0x0FFF FFFF to 0x0D00 0000
0x0CFF FFFF to 0x0C00 0000
0x0BFF FFFF to 0x0B00 0000
0x0AFF FFFF to 0x0A00 0000
0x09FF FFFF to 0x0400 0000
0x03FF FFFF to 0x0000 0000
4.2.1 ROM space
The ROM space mapping differs depending on the capacity of the ROM being used. The ROM capacity is set via
the ROMs(1:0) bits in the BCUCNTREG1 register.
The physical addresses of the ROM space are listed below.
Physical address
0x1FFF FFFF to 0x1FC0 0000
0x1FBF FFFF to 0x1F80 0000
0x1F7F FFFF to 0x1F40 0000
0x1F3F FFFF to 0x1F00 0000
0x1EFF FFFF to 0x1E80 0000
0x1E7F FFFF to 0x1E00 0000
4.2.2 External system bus space
The following two types of system bus space are available.
• External system bus I/O space
This corresponds to the ISA's I/O space.
• External system bus memory space
This corresponds to the ISA's memory space.
CHAPTER 4 MEMORY MANAGEMENT SYSTEM
Table 4-1. V
4181 Physical Address Space
R
Space
Mirror image of 0x1FFF FFFF to 0x0000 0000
ROM space
External system bus I/O space (ISA I/O)
External system bus memory space (ISA memory)
Space reserved for future use
Internal ISA I/O space 1
Internal ISA I/O space 2
MBA bus I/O space
Space reserved for future use
DRAM (SDRAM) space
Table 4-2. ROM Address Map
When using 32-Mbit ROM
Bank 3 (ROMCS3#)
Bank 2 (ROMCS2#)
Bank 1 (ROMCS1#)
Bank 0 (ROMCS0#)
Reserved for future use
User's Manual U14272EJ3V0UM
Capacity (bytes)
3.5 G
128 M
64 M
64 M
48 M
16 M
16 M
16 M
96 M
64 M
When using 64-Mbit ROM
Bank 3 (ROMCS3#)
Bank 2 (ROMCS2#)
Bank 1 (ROMCS1#)
Bank 0 (ROMCS0#)
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