Cp0 Registers - NEC VR4181 mPD30181 User Manual

1.4.4 CP0 registers

The CP0 has thirty-two registers, each of which has its own register number.
Table 1-6 shows simple descriptions of each register. For the detailed descriptions of the registers, refer to
CHAPTER 3 CP0 REGISTERS.
Table 1-6. System Control Coprocessor (CP0) Register Definitions
Number Register
0 Index
1 Random
2 EntryLo0
3 EntryLo1
4 Context
5 PageMask
6 Wired
−
7
8 BadVAddr
9 Count
10 EntryHi
11 Compare
12 Status
13 Cause
14 EPC
15 PRId
16 Config
Note1
17 LLAddr
18 WatchLo
19 WatchHi
20 XContext
−
21 to 25
Note2
26 Parity Error
Note2
27 Cache Error
28 TagLo
29 TagHi
30 ErrorEPC
−
31
Notes1. This register is defined to maintain compatibility with the V
meaningless during normal operations.
2. This register is defined to maintain compatibility with the V
hardware.
CHAPTER 1 INTRODUCTION
Usage
Memory management Programmable pointer to TLB array
Memory management Pseudo-random pointer to TLB array (read only)
Memory management Lower half of TLB entry for even VPN
Memory management Lower half of TLB entry for odd VPN
Exception processing Pointer to kernel virtual PTE in 32-bit mode
Memory management Page size specification
Memory management Number of wired TLB entries
−
Reserved for future use
Exception processing Virtual address where the most recent error occurred
Exception processing Timer count
Memory management Higher half of TLB entry (including ASID)
Exception processing Timer compare value
Exception processing Status indication
Exception processing Cause of last exception
Exception processing Exception Program Counter
Memory management Processor revision identifier
Memory management Configuration (memory system modes) specification
Memory management Physical address for self diagnostics
Exception processing Memory reference trap address low bits
Exception processing Memory reference trap address high bits
Exception processing Pointer to kernel virtual PTE in 64-bit mode
−
Reserved for future use
Exception processing Cache parity bits
Exception processing Index and status of cache error
Memory management Lower half of cache tag
Memory management Higher half of cache tag
Exception processing Error Exception Program Counter
−
Reserved for future use
User's Manual U14272EJ3V0UM
Description
TM
4000 and V 4400
R R
TM
4100 . This register is not used in the V
R
TM
. This register is
4181
R
43