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3.2.4 Context register (4)
The Context register is a read/write register containing the pointer to an entry in the page table entry (PTE) array
on the memory; this array is a table that stores virtual-to-physical address translations. When there is a TLB miss,
the operating system loads the unsuccessfully translated entry from the PTE array to the TLB. The Context register
is used by the TLB Refill exception handler for loading TLB entries.
The Context register duplicates some of the information provided in the BadVAddr register, but the information is
arranged in a form that is more useful for a software TLB exception handler.
31
PTEBase
63
PTEBase: The PTEBase field is a base address of the PTE entry table.
BadVPN2: This field holds the value (VPN2) obtained by halving the virtual page number of the most recent
virtual address for which translation failed.
0:
Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
The PTEBase field is used by software as the pointer to the base address of the PTE table in the current user
address space.
The 21-bit BadVPN2 field contains bits 31 to 11 of the virtual address that caused the TLB miss; bit 10 is excluded
because a single TLB entry maps to an even-odd page pair. For a 1 KB page size, this format can directly address
the pair-table of 8-byte PTEs. When the page size is 4 KB or more, shifting or masking this value produces the
correct PTE reference address.
CHAPTER 3 CP0 REGISTERS
Table 3-2. Cache Algorithm
C bit value
0
Cached
1
Cached
2
Uncached
3
Cached
4
Cached
5
Cached
6
Cached
7
Cached
Figure 3-4. Context Register
(a) 32-bit mode
25
24
BadVPN2
(b) 64-bit mode
25
PTEBase
User's Manual U14272EJ3V0UM
Cache algorithm
4
24
4
BadVPN2
3
0
0
3
0
0
71
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