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10.6.7 Exiting Suspend mode (EDO DRAM)
<1> Generate a wake-up event from Suspend mode such as a transition on the POWER pin, a DCD interrupt,
etc.
<2> Software execution resumes at the General exception vector (0x0BFC 0380 when BEV = 1).
<3> Copy the codes for the restore (<4> through <8> below) beginning at a 16-byte boundary into the cache
by using a Fill operation of CACHE instruction, and jump to the cached codes. These codes can be
executed on ROM.
<4> Poll the OK_STOP_CLK bit in the DRAMHIBCTL register until it is set to 1.
Remark Software must wait until the OK_STOP_CLK bit in the DRAMHIBCTL register is set to 1 before
reinitializing the memory controller registers. Otherwise unpredictable behavior of the memory
controller could result.
<5> Clear the DRAM_EN bit in the DRAMHIBCTL register to 0 so that the DRAM interface signals are again
driven directly by the memory controller.
<6> Clear SUSPEND bit in the DRAMHIBCTL register to 0 to exit self-refresh mode.
<7> If DRAM can accept mixed use of burst and distributive CBR refresh, set a value that determines the
refresh count to every 250 ns to the BCURFCNTREG register in the MBA Host Bridge. Then execute
CBR refresh cycles for a specific time period (i.e. 0x3FFF × TClock period + burst refresh interval
required by DRAM).
<8> Restore to the BCURFCNTREG register in the MBA Host Bridge a value that determines refresh interval
satisfying the conditions of DRAM type to be used.
10.6.8 Exiting Suspend mode (SDRAM)
<1> Generate a wake-up event from Suspend mode such as a transition on the POWER pin, a DCD interrupt,
etc.
<2> Software execution resumes at the General exception vector (0x0BFC 0380 when BEV = 1).
<3> Copy the codes for the restore (<4> through <7> below) beginning at a 16-byte boundary into the cache
by using a Fill operation of CACHE instruction, and jump to the cached codes. These codes can be
executed on ROM.
<4> Clear the DRAM_EN bit in the DRAMHIBCTL register to 0 so that the DRAM interface signals are again
driven directly by the memory controller.
<5> SDRAM exits the self-refresh mode.
<6> If burst refreshes are needed, set a value that determines the refresh count to every 250 ns to the
BCURFCNTREG register in the MBA Host Bridge. Then execute CBR auto refresh cycles for a specific
time period (i.e. 0x3FFF × TClock period + burst refresh interval required by DRAM).
<7> Restore to the BCURFCNTREG register in the MBA Host Bridge a value that determines refresh interval
satisfying the conditions of DRAM type to be used.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU)
User's Manual U14272EJ3V0UM
207
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