Mixed Memory Mode (Edo Dram Only); Edo Dram Timing Parameters - NEC VR4181 mPD30181 User Manual

6.4.2 Mixed memory mode (EDO DRAM only)

The MEMCFG_REG register provides two bits each for Bank 0 and Bank 1 to set types of DRAMs to be used.
This allows the two banks to be configured with different types of DRAMs, for example, Bank 0 can be mapped on 64
Mbit devices and Bank 1 on 16 Mbit devices, to optimize the cost of the total memory required.
16 Mbits
16 Mbits
64 Mbits
16 Mbits
64 Mbits
64 Mbits

6.4.3 EDO DRAM timing parameters

The following table shows examples of EDO DRAM timing parameters when using EDO DRAMs with access time
of 60 ns. These parameters are set in EDOMCYTREG register.
TClock RAS to CAS
frequency delay
66 MHz 3 TClock
50 MHz 2 TClock
33 MHz 2 TClock
25 MHz 2 TClock
CHAPTER 6 BUS CONTROL
Table 6-2. V 4181 EDO DRAM Capacity
R
Bank 0
0
16 Mbits
0
64 Mbits
16 Mbits
64 Mbits
CAS pulse CAS precharge
width
1 TClock 1 TClock
1 TClock 1 TClock
1/2 TClock 1/2 TClock
1/2 TClock 1/2 TClock
User's Manual U14272EJ3V0UM
Bank 1 Total DRAM capacity
2 MB
4 MB
8 MB
10 MB
10 MB
16 MB
RAS precharge
3 TClock
2 TClock
2 TClock
1 TClock
RAS pulse Self refresh
width RAS precharge
3 TClock 8 TClock
3 TClock 6 TClock
2 TClock 4 TClock
2 TClock 3 TClock
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