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10.6.4 Exiting Hibernate mode (SDRAM)
<1> Generate a wake-up event such as a transition on the POWER pin, a DCD interrupt, etc. which causes
the PMU to start a power-on sequence.
<2> Apply 2.5 V power supply when the MPOWER signal becomes high level. The PMU waits until 3.3 V and
2.5 V power supply are stable, and then deasserts the reset signals to the V
peripheral units.
<3> Software execution resumes at the Cold Reset exception vector (0x0BFC 0000). Initialize the cache tags,
and the Config, Status, and WatchLo registers in the CP0. Reset the HALTimer by setting the
HALTIMERRST bit in the PMUCNTREG register to 1.
<4> Check and clear the TIMOUTRST bit in the PMUINTREG register in the case a HALTimer Shutdown had
occurred.
<5> Copy the codes for the restore (<6> through <12> below) beginning at a 16-byte boundary into the cache
by using a Fill operation of CACHE instruction, and jump to the cached codes. These codes can be
executed on ROM.
<6> Reinitialize all the registers and peripherals during Hibernate mode and restore those registers saved in
the general-purpose registers, MISCREG(0:15) which retain values during Hibernate mode, in the GIU or
in external memory.
<7> Clear the DRAM_EN bit in the DRAMHIBCTL register to 0 so that the DRAM interface signals are again
driven directly by the memory controller.
<8> SDRAM exits the self-refresh mode.
<9> Set the MEMCFG_REG, MODE_REG, and SDTIMINGREG registers in the memory controller according
to the SDRAM type to be used.
<11> If burst refreshes are needed, set a value that determines the refresh count to every 250 ns to the
BCURFCNTREG register in the MBA Host Bridge. Then execute CBR auto refresh cycles for a specific
time period (i.e. 0x3FFF × TClock period + burst refresh interval required by DRAM).
<12> Restore to the BCURFCNTREG register in the MBA Host Bridge a value that determines refresh interval
satisfying the conditions of DRAM type to be used.
204
CHAPTER 10 POWER MANAGEMENT UNIT (PMU)
User's Manual U14272EJ3V0UM
4110 CPU core and on-chip
R
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