NEC VR4181 mPD30181 User Manual page 168

64-/32-bit microprocessor hardware
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Bit
Name
2
RXBEINT
1
RXFFINT
0
RXBSYINT
168
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI)
Receive Burst End interrupt request status
0 : Not pending
1 : Pending
This bit is cleared by writing 1.
Receive FIFO Full interrupt request status
0 : Not pending
1 : Pending
This bit is cleared by writing 1.
Receive Shift Register Busy interrupt request status
0 : Not pending
1 : Pending
This bit is cleared by writing 1.
User's Manual U14272EJ3V0UM
Function
(2/2)

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