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6.7.1 ISABRGCTL (0x0B00 02C0)
Bit
15
Name
Reserved
R/W
R
RTCRST
0
Other resets
0
Bit
7
Name
Reserved
R/W
R
RTCRST
0
Other resets
0
Bit
Name
15 to 2
Reserved
1, 0
PCLKDIV(1:0)
This register is used to set the PCLK divisor rate. PCLK is a clock for internal ISA peripherals, and its frequency
must be set to between 18.432 MHz and 33 MHz.
138
CHAPTER 6 BUS CONTROL
14
13
Reserved
Reserved
Reserved
R
R
0
0
0
0
6
5
Reserved
Reserved
Reserved
R
R
0
0
0
0
0 is returned when read
PCLK (peripheral clock) divisor rate selection. These bits select the operating
frequency of PCLK.
00 : TClock / 8
01 : TClock / 4
10 : TClock / 2
11 : TClock / 1
User's Manual U14272EJ3V0UM
12
11
10
Reserved
Reserved
R
R
R
0
0
0
0
0
0
4
3
2
Reserved
Reserved
R
R
R
0
0
0
0
0
0
Function
9
8
Reserved
Reserved
R
R
0
0
0
0
1
0
PCLKDIV1
PCLKDIV0
R/W
R/W
0
0
0
0
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