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10.3.2 RSTSW reset
When the RSTSW# signal becomes active, the PMU resets (Cold Reset) the CPU core. When bit 6 of the
PMUINTREG register is cleared to 0, the PMU also resets all internal peripheral units except for the RTC and GIU.
In addition, the RSTSW bit in the PMUINTREG register is set to 1. After the CPU core is restarted, the RSTSW bit
must be checked and cleared to 0 by software.
For details of the timing of RSTSW reset, refer to CHAPTER 5 INITIALIZATION INTERFACE.
10.3.3 Deadman's Switch reset
When the Deadman's Switch function is enabled, software must write 1 to DSWCLR bit in the DSUCLRREG
register each set time, to clear the Deadman's Switch counter (for more information, refer to CHAPTER 12
DEADMAN'S SWITCH UNIT (DSU)).
If the Deadman's Switch counter is not cleared within the set time, the PMU resets all peripheral units except for
RTC, GIU, and PMU. Then the PMU resets (Cold Reset) the CPU core.
In addition, DMSRST bit in the PMUINTREG register is set to 1. After the CPU core is restarted, DMSRST bit must
be checked and cleared to 0 by software.
10.3.4 Preserving DRAM data on RSTSW reset
(1) Preserving EDO-DRAM data
When an RSTSW reset takes place, the PMU activates the CAS#/RAS# pins to generate a CBR self refresh
request to EDO DRAM.
Remark
There is no burst CBR refresh before and after CBR self refresh by RSTSW reset.
Figure 10-2. EDO DRAM Signals on RSTSW Reset (SDRAM Bit = 0)
RTC (Internal)
RSTSW# (Input)
CAS# (Output)
RAS(1:0)# (Output)
(2) Preserving SDRAM data
The SDRAM bit of the PMUINTREG register can be used to preserve the contents of SDRAM connected to the
V
4181 during an RSTSW reset. When the SDRAM bit is set to 1, the PMU does not reset the memory controller.
R
Therefore, the memory controller completes current SDRAM access and performs CBR refresh cycle on an
RSTSW reset. On the other hand, when the SDRAM bit is set to 0, the memory controller is reset regardless of
accesses under processing and does not perform CBR refresh cycle (SDRAM data will be destroyed).
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CHAPTER 10 POWER MANAGEMENT UNIT (PMU)
User's Manual U14272EJ3V0UM
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