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(4) Shift clock
The shift clock (SHCLK) edges can be programmed only indirectly. The SHCLK is also output in rows of the
vertical blank if the DummyL bit of the VRVISIBREG register is 1. The position of SHCLK edges are controlled by
the Panelcolor and PanDbus bits of the LCDCFGREG0 register. The SCLKPOL bit of the LCDCTRLREG register
determines whether data is latched into the panel on the rising or falling edges. If the SCLKPOL bit is 0, data is
latched on the falling edges.
(5) M signal
Some panels also need a modulation signal, M, to operate properly. The modulation rate is controlled by
MOD(7:0) bits of the LCDCFGREG0 register. If the MOD field is 0, the M signal toggles once per frame. If the
MOD field is not 0, then the M signal toggles once every rows set in the MOD field. The M signal toggles at the
position specified in the LCE field, the same time as the second LOCLK edge. When the MOD field is 0, the M
signal toggles when the LOCLK latches the FLM.
(6) Vertical retrace interrupt
When the LCD controller goes through the vertical blank, a status signal bit VIReq of the LCDINRQREG register
becomes 1. This signal can be configured to be polled or to generate an interrupt request. To enable the
interrupt, set the MVIReq bit of the LCDIMSKREG register to 1. Once an interrupt request is generated, writing to
the VIReq bit clears the interrupt request. However, the state of the VIReq bit changes to 0 only after the
controller returns to top left corner. Note that there is some delay between the controller's entering or leaving the
vertical blank and the changes in the VIReq bit.
21.3.2 Controller clocks
All LCD controller timing is based on the internal clock hpck. The hpck is derived from the gclk, which is derived
from the MBA clock (TClock). The frequency of gclk can be equal to, one-half of, or one-quarter of that of the MBA
clock, depending on the Pre-scal(1:0) bits of the LCDCFGREG0 register and the MBA clock frequency. The hpck
frequency is programmable. In each cycle the hpck is at high level for cycles set in the HpckH(5:0) bits of the
LCDCFGREG1 register, and at low level for cycles set in the HpckL(5:0) bits of the LCDCFGREG1 register. The
values in HpckH and HpckL fields are not arbitrary. Their sum must be at least 5, and the following condition must be
satisfied:
f-hpck ≈ Htotal x Vtotal x f-refresh
Both the hpck and the gclk can be turned off when the panel is inactive. Setting the ContCkE bit of the
LCDCTRLREG register to 1 initializes the LCD controller and turns on both clocks, or 0 turns them off.
CHAPTER 21 LCD CONTROLLER
User's Manual U14272EJ3V0UM
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