NEC VR4181 mPD30181 User Manual page 162

64-/32-bit microprocessor hardware
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Bit
Name
7
FRMMD
6
CKPOL
5
CKMD
4 to 1
Reserved
0
LSBMSB
Note The TXCLR and RXCLR bits must be cleared after changing the CKPOL or CKMD bit.
The CKPOL bit must be set as follows according to the state of SCK when a communication is not performed:
• When SCK is at low level during no communication ... CKPOL bit = 0
• When SCK is at high level during no communication ... CKPOL bit = 1
162
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI)
FRM mode
0 : FRM controls transfer directions (receive when FRM= 1, transmit when FRM=
0)
1 : FRM enables transfers (transmit/receive enabled when FRM = 0)
CSI clock polarity
0 : SCK is active high (1st transition is low to high)
1 : SCK is active low (1st transition is high to low)
CSI clocking mode
0 : Character data is valid prior to the 1st transition of SCK
1 : Character data is valid at the 1st transition of SCK
0 is returned after read
Transmit/receive mode bit ordering
0 : Bit 7 is the first bit transmitted or received (MSB mode)
1 : Bit 0 is the first bit transmitted or received (LSB mode)
User's Manual U14272EJ3V0UM
Function
Note
Note
(2/2)

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