Table of Contents
Advertisement
3.2.18 XContext register (20)
The read/write XContext register contains a pointer to an entry in the page table entry (PTE) array, an operating
system data structure that stores virtual-to-physical address translations. If a TLB miss occurs, the operating system
loads the untranslated data from the PTE into the TLB to handle the software error.
The XContext register is used by the XTLB Refill exception handler to load TLB entries in 64-bit addressing mode.
The XContext register duplicates some of the information provided in the BadVAddr register, and puts it in a form
useful for the XTLB exception handler.
This register is included solely for operating system use. The operating system sets the PTEBase field in the
register, as needed.
63
PTEBase: Base address of the PTE entry table.
Space type (00 → User, 01→ Supervisor, 11 → Kernel). The setting of this field matches virtual
R:
address bits 63 and 62.
BadVPN2: The value (VPN2) obtained by halving the virtual page number of the most recent virtual address
for which translation failed.
0:
Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
The 29-bit BadVPN2 field has bits 39 to 11 of the virtual address that caused the TLB miss; bit 10 is excluded
because a single TLB entry maps to an even-odd page pair. For a 1 KB page size, this format may be used directly
to address the pair-table of 8-byte PTEs. When the page size is 4 KB or more, shifting or masking this value
produces the appropriate PTE reference address.
86
CHAPTER 3 CP0 REGISTERS
Figure 3-22. XContext Register
35 34 33
PTEBase
R
User's Manual U14272EJ3V0UM
32
4
3
BadVPN2
0
0
Advertisement
Table of Contents
