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17.4.19 DTGENCLREG (Index: 0x16)
Bit
7
Name
Reserved
R/W
R
Reset
0
Bit
Name
7, 6
Reserved
5
SWCDINT
4
CDRSMEN
3, 2
Reserved
1
CFGRSTEN
0
DLY16INH
The functionality and acknowledgment of this software interrupt request operate in the same way as those of the
hardware-generated interrupt requests. The functionality and acknowledgement of the hardware card detect or card
status change interrupt request are not affected by the setting of the SWCDINT bit. If card detect or card status
change is signaled through the CD1# and CD2# inputs, a hardware card detect or card status change interrupt
request is generated.
When the CDRSMEN bit is set to 1, the RIO# signal (internal) goes from high level to low and the CD_CHG bit in
the CDSTCHGREG register is set to 1. The RIO# signal remains low until either a read or a write of 1 to the CD_CHG
bit (acknowledge cycle), which causes the CD_CHG bit to be reset to 0 and the RIO# signal to go from low level to
high. If the card status change is routed to any of the IRQ signals, the setting of this bit to 1 prevents the IRQ signal
from going active as a result of a hardware card detect status change. Once the software detects a card detect status
change interrupt request from the RIO# signal by reading the CDSTCHGREG register, it must issue a software card
detect change interrupt request so that the card detect change condition generates an active interrupt request on the
IRQ signal.
CHAPTER 17 COMPACTFLASH CONTROLLER (ECU)
6
5
Reserved
SWCDINT
CDRSMEN
R
W
0
0
0 is returned when read
Software card detect interrupt request
1 : Generates interrupt request
This bit is valid when the CD_EN bit is set to 1 in the CRDSTATREG register. 0 is
returned when read.
Card detect resume enable
1 : Enables notification of change on CD1# and CD2# inputs
This bit is valid when the CD_EN bit is set to 1 in the CRDSTATREG register. 0 is
returned when read.
0 is returned when read
Configuration reset enable
1 : Enables initializing registers on high level of both CD1# and CD2# inputs
The registers involved are all I/O registers, all memory registers, ITGENCTREG
register, and ADWINENREG register.
16-bit memory delay prohibit. This bit is used to set whether the falling edge of
the WE# and OE# (CF_WE# and CF_OE#) signals of the CompactFlash is
delayed in synchronization with SYSCLK when a memory window is set to be 16
bit in the DWIDTH bit of the MEMWIDn_REG register.
0 : Delayed
1 : Not delayed
User's Manual U14272EJ3V0UM
4
3
Reserved
Reserved
R/W
R
0
0
Function
2
1
0
CFGRSTEN
DLY16INH
R
R/W
R/W
0
0
0
347
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