Mode_Reg (0X0A00 0308) - NEC VR4181 mPD30181 User Manual

6.5.3 MODE_REG (0x0A00 0308)

Bit 15
Name Reserved
R/W R
At reset 0
Bit 7
Name TE-Ven2
R/W R/W
At reset 0
Bit Name
15 to 12 Reserved
11, 10 0
9 BR-SW
8, 7 TE-Ven(1:2)
6 to 4 LTMode(2:0)
3 WT
2 to 0 BL(2:0)
Note The CAS latency mode must be set according to the operation frequency of the SDCLK (SDRAM clock).
This register is used to set the value output to ADD(13:0) pins during the SDRAM mode register setting cycle. This
register should be written before the Init bit of MEMCFG_REG register is set to 1.
CHAPTER 6 BUS CONTROL
14 13
Reserved Reserved Reserved
R R
0 0
6 5
LTMode2 LTMode1 LTMode0
R/W R/W
0 0
0 is returned when read
These bits should be always written to 00.
Burst read - single write
This bit should be always written to 0.
These two bits define a JEDEC test cycle and vendor specific cycles.
These bits should be always written to 00.
CAS latency mode
010 : 2 clocks
011 : 3 clocks
Others : Reserved
Wrap type for the burst cycles. This bit should be always written to 0.
0 : Sequential (default)
Burst length. These bits should be always written to 111.
111 : Full page (When WT = 0 only. Setting prohibited when WT = 1)
User's Manual U14272EJ3V0UM
12 11
0
R R/W R/W
0 0
4 3
WT BL2
R/W R/W R/W
0 0
Function
Note
10 9
0 BR-SW TE-Ven1
R/W R/W
0 0
2 1
BL1 BL0
R/W R/W
0 0
8
0
0
0
135