Rom Interface; External Rom Devices Memory Mapping - NEC VR4181 mPD30181 User Manual

6.3 ROM Interface

The V 4181 supports three ROM modes, ordinary ROM, PageROM, and flash memory. The mode setting is made
R
via the BCUCNTREG1 register's Rtype(1:0) bits and ROMWEN0 bit. Access speed setting in ordinary ROM or
PageROM mode is made via the BCUSPEEDREG register.
Remark The V 4181 supports only 16-bit access for external ROM devices.
R

6.3.1 External ROM devices memory mapping

Physical address
0x1FFF FFFF to 0x1FC0 0000
0x1FBF FFFF to 0x1F80 0000
0x1F7F FFFF to 0x1F40 0000
0x1F3F FFFF to 0x1F00 0000
0x1EFF FFFF to 0x1E80 0000
0x1E7F FFFF to 0x1E00 0000
Bank 3 contains boot vector and has a dedicated pin for chip select (ROMCS3#). Chip select pins for Bank 2, 1,
and 0, ROMCS(2:0)#, are alternated with general-purpose I/O signals and are defined as general-purpose inputs
after RTC reset. Set GPMD2REG and GPMD3REG registers in the GIU to use them as ROMCS(2:0)#.
118
CHAPTER 6 BUS CONTROL
32 Mbit ROM
Bank 3 (ROMCS3#)
Bank 2 (ROMCS2#)
Bank 1 (ROMCS1#)
Bank 0 (ROMCS0#)
Reserved
Reserved
User's Manual U14272EJ3V0UM
64 Mbit ROM
Bank 3 (ROMCS3#)
Bank 2 (ROMCS2#)
Bank 1 (ROMCS1#)
Bank 0 (ROMCS0#)