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NEC PD750004 User Manual

4 bit single-chip microcomputer
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USER'S MANUAL
4 BIT SINGLE-CHIP MICROCOMPUTER
©
1995
µPD750008
µPD750004
µPD750006
µPD750008
µPD75P0016
Document No. U10740EJ2V0UM00 (2nd edition)
(Previous No. IEU-1421)
Date Published April 1996 P
Printed in Japan

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Summary of Contents for NEC PD750004

  • Page 1 USER'S MANUAL 4 BIT SINGLE-CHIP MICROCOMPUTER © 1995 µPD750008 Document No. U10740EJ2V0UM00 (2nd edition) (Previous No. IEU-1421) Date Published April 1996 P Printed in Japan µPD750004 µPD750006 µPD750008 µPD75P0016...
  • Page 2 FEATURES OF THE ARCHITECTURE AND MEMORY MAP PERIPHERAL HARDWARE FUNCTIONS INTERRUPT AND TEST FUNCTIONS WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016 MASK ROM ORDERING PROCEDURE GENERAL PIN FUNCTIONS INTERNAL CPU FUNCTIONS STANDBY FUNCTION RESET FUNCTION MASK OPTION INSTRUCTION SET...
  • Page 3 The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
  • Page 4 Page The 44-pin plastic QFP package has been changed from µPD750008GB-xxx-3B4 to µPD750008GB-xxx-3BS-MTX. The µPD75P0016 under development has been changed to the already-developed µPD75P0016. The input withstand voltage at ports 4 and 5 during open drain has been changed from 12 V to 13 V.
  • Page 5 –> See the instruction index in Appendix D. • To check the functions of specific internal circuits, etc.: –> See Appendix E. • To understand the overall functions of the µPD750004, µPD750006, µPD750008, and µPD75P0016: –> Read through all chapters sequentially. PREFACE...
  • Page 6 Notation Data bit significance Active low Memory map address Note Caution Remark Important and emphasized matter : Described in bold face Numeric value : Higher-order bits on the left side Lower-order bits on the right side : xxx (Pin and signal names are overscored.) : Low-order address on the upper side High-order address on the lower side : Explanation of an indicated part of text...
  • Page 7 Document Name Package Manual Semiconductor Device Mounting Technology Manual Quality Grade on NEC Semiconductor Devices Reliability and Quality Control of NEC Semiconductor Devices Electrostatic Discharge (ESD) Test Semiconductor Device Quality Guarantee Guide Microcontroller-Related Products Guide - by third parties Caution The above related documents are subject to change without notice. Be sure to use the latest edition when you design your system.
  • Page 8 [MEMO]...

  • Page 9: Table Of Contents

    INT2 ... KR0-KR3 ... KR4-KR7 ... X1, X2 ... XT1, XT2... RESET ... DD ... SS ... IC (for the µPD750004, µPD750006, and µPD750008 only) ... (for the µPD75P0016 only) ... MD0-MD3 (for the µPD75P0016 only) ... - i -...
  • Page 10 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP ... DATA MEMORY BANK STRUCTURE AND ADDRESSING MODES ... 3.1.1 3.1.2 GENERAL REGISTER BANK CONFIGURATION ... MEMORY-MAPPED I/O ... CHAPTER 4 INTERNAL CPU FUNCTIONS ... Mk I MODE/Mk II MODE SWITCH FUNCTIONS ... 4.1.1 4.1.2 PROGRAM COUNTER (PC) ...
  • Page 11 5.3.5 5.3.6 CLOCK TIMER ... 105 5.4.1 5.4.2 TIMER/EVENT COUNTER ... 108 5.5.1 5.5.2 5.5.3 SERIAL INTERFACE ... 123 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 5.6.8 BIT SEQUENTIAL BUFFER ... 181 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS ... 183 CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT ...
  • Page 12 CHAPTER 8 RESET FUNCTION ... 225 CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) ... 229 OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY ... 230 WRITING TO THE PROGRAM MEMORY ... 230 READING THE PROGRAM MEMORY ... 232 SCREENING OF ONE-TIME PROM ...
  • Page 13 APPENDIX A FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016 ... 299 APPENDIX B DEVELOPMENT TOOLS ... 301 APPENDIX C MASKED ROM ORDERING PROCEDURE ... 309 APPENDIX D INSTRUCTION INDEX ... 311 INSTRUCTION INDEX (BY FUNCTION) ... 311 INSTRUCTION INDEX (ALPHABETICAL ORDER) ... 314 APPENDIX E HARDWARE INDEX ...
  • Page 14 General Register Configuration (8-bit Processing) ... µPD750008 I/O Map ... Stack Bank Selection Register Format ... Program Counter Organization ... Program Memory Map (in µPD750004) ... Program Memory Map (in µPD750006) ... Program Memory Map (in µPD750008) ... Program Memory Map (in µPD75P0016)...
  • Page 15 Figure No. I/O Timing Chart of Digital I/O Ports ... 5-10 ON Timing Chart of Built-in Pull-Up Resistor Connected by Software ... 5-11 Block Diagram of the Clock Generator ... 5-12 Format of the Processor Clock Control Register ... 5-13 Format of the System Clock Control Register ...
  • Page 16 Figure No. 5-45 Operations of RELT and CMDT ... 141 5-46 Transfer Bit Switching Circuit ... 141 5-47 Example of Two-Wire Serial I/O System Configuration ... 144 5-48 Timing of Two-Wire Serial I/O Mode... 147 5-49 Operations of RELT and CMDT ... 148 5-50 Example of SBI System Configuration ...
  • Page 17 Figure No. 5-81 Format of the Bit Sequential Buffer ... 181 Block Diagram of Interrupt Control Circuit ... 184 Interrupt Vector Table ... 185 Interrupt Priority Specification Register ... 189 Configurations of the INT0, INT1, and INT4 Circuits ... 191 I/O Timing of a Noise Eliminator ...
  • Page 18 Table No. Features of the Products ... Digital I/O Port Pins ... Non-Port Pin Functions ... Connection of Unused Pins ... Addressing Modes ... Register Bank to Be Selected with the RBE and RBS... Recommended Use of Register Banks with Normal Routines and Interrupt Routines ...
  • Page 19 Table No. Operation Statuses in the Standby Mode ... 216 Selection of a Wait Time with BTM ... 219 Status of the Hardware after a Reset ... 226 10-1 Selecting Mask Option of Pin ... 235 LIST OF TABLES (2/2) Title - xi - Page...
  • Page 20 [MEMO] - xii -...

  • Page 21: Chapter 1 General

    The µPD750004, µPD750006, µPD750008, and µPD75P0016 are 75XL series 4-bit single-chip microcom- puters. The 75XL series is a successor of the 75X series consisting of many products. These µPD750004, µPD750006, µPD750008, and µPD75P0016 are collectively called the µPD750008 subseries. The 75XL series takes over the CPUs of the 75X series, realizing a wide range of operating voltages and high-speed operation.

  • Page 22: Function Overview

    • 0.67, 1.33, 2.67, 10.7 µs (when the main system clock operates at 6.0 MHz) • 122 µs (when the subsystem clock operates at 32.768 kHz) Internal memory ROM 4096 x 8 bits (µPD750004) 6144 x 8 bits (µPD750006) 8192 x 8 bits (µPD750008) 16384 x 8 bits (µPD75P0016)

  • Page 23: Ordering Information

    ORDERING INFORMATION Part number µPD750004CU-xxx Note µPD750004GB-xxx-3BS-MTX µPD750006CU-xxx µPD750006GB-xxx-3BS-MTX Note µPD750008CU-xxx Note µPD750008GB-xxx-3BS-MTX µPD75P0016CU Note µPD75P0016GB-3BS-MTX Note Code orders on and after April 1, 1996 can be accepted. Remark xxx is a ROM code number. Package 42-pin plastic shrink DIP (600 mil) 44-pin plastic QFP (10 x 10 mm) 42-pin plastic shrink DIP (600 mil) 44-pin plastic QFP (10 x 10 mm)

  • Page 24: Differences Among Subseries Products

    ROM model. If you replace the PROM model with the ROM model of the course of experimental production to mass production, perform thorough evaluation by using the CS model (not ES model) of the mask ROM model. µPD750004 µPD750006 12 bits...

  • Page 25: Block Diagram

    INT4 control KR0 - KR7 Notes 1. The program counter for the µPD750004 consists of 12 bits, 13 bits for the µPD750006 and µPD750008, and 14 bits for the µPD75P0016. 2. The ROM capacity depends on the product. 3. ( ) : µPD75P0016...

  • Page 26: Pin Configuration (Top View)

    µPD750008 USER'S MANUAL PIN CONFIGURATION (TOP VIEW) (1) 42-pin plastic shrink DIP (600 mil) µPD750004CU-XXX µPD750006CU-XXX µPD750008CU-XXX µPD75P0016CU RESET P33 (/MD3) P32 (/MD2) P31 (/MD1) P30 (/MD0) SI/SB1/P03 SO/SB0/P02 SCK/P01 INT4/P00 TI0/P13 INT2/P12 INT1/P11 INT0/P10 Note IC (V Note Connect IC (V ) to V Remark ( ) : µPD75P0016.
  • Page 27 (2) 44-pin plastic QFP (10 x 10 mm) µPD750004GB-XXX-3BS-MTX µPD750006GB-XXX-3BS-MTX µPD750008GB-XXX-3BS-MTX µPD75P0016GB-3BS-MTX P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 Note Connect IC (V ) to V Remark ( ) : µPD75P0016. 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 , keeping the wiring as short as possible.
  • Page 28 µPD750008 USER'S MANUAL Pin name P00-P03 : Port 0 P10-P13 : Port 1 P20-P23 : Port 2 P30-P33 : Port 3 P40-P43 : Port 4 P50-P53 : Port 5 P60-P63 : Port 6 P70-P73 : Port 7 P80-P81 : Port 8 KR0-KR7 : Key return : Serial clock : Serial input...

  • Page 29: Chapter 2 Pin Functions

    CHAPTER 2 PIN FUNCTIONS 2.1 PIN FUNCTIONS OF THE µPD750008 Table 2-1. Digital I/O Port Pins (1/2) Also Input/ used output Input INT4 SO/SB0 SI/SB1 Input INT0 INT1 INT2 PTO0 PTO1 Note 2 Note 3 (MD0) Note 2 Note 3 (MD1) Note 2 Note 3...
  • Page 30 µPD750008 USER'S MANUAL Also Input used output P40- — Note 2, 4 P50- — Note 2, 4 — — Notes 1. I/O circuits enclosed in circles have a Schmitt-triggered input. 2. An LED can be driven directly. 3. ( ): µPD75P0016 4.

  • Page 31: Non-Port Pin Functions

    Also Input/ used output Input Inputs external event pulse to the timer/event counter PTO0 Timer/event counter output PTO1 Timer counter output Clock output Fixed frequency output (for buzzer or system clock trimming) Serial clock I/O SO/SB0 Serial data output or serial data bus I/O SI/SB1 Serial data input or serial data bus I/O INT4...

  • Page 32: Pin Functions

    µPD750008 USER'S MANUAL 2.2 PIN FUNCTIONS 2.2.1 P00-P03 (PORT0) : Input Pins Used Also for INT4, SCK, SO/SB0 and SI/SB1 P10-P13 (PORT1) : Input Pins Used Also for INT0-INT2, and TI0 These are the input pins of the 4-bit input ports: Ports 0 and 1. Ports 0 and 1 function as input ports, and also have the functions described below.

  • Page 33: P20-P23 (Port2)

    2.2.2 P20-P23 (PORT2) : I/O Pins Used Also for PTO0, PTO1, PCL, and BUZ P30-P33 (PORT3) : I/O Pins Used Also for MD0-MD3 P40-P43 (PORT4), P50-P53 (PORT5) : N-ch Open-Drain Intermediate Withstand Voltage (13 V) Large-Current Output P60-P63 (PORT6), P70-P73 (PORT7) : Tristate I/O These pins are the I/O pins of the 4-bit I/O ports with output latches: Ports 2 to 7.

  • Page 34: Pcl

    µPD750008 USER'S MANUAL 2.2.6 PCL: Output Pin Used Also for Port 2 This is the programmable clock output pin. It is used to supply the clock pulse to a peripheral LSI circuit such as a slave microcomputer or A/D converter. A RESET signal clears the clock mode register (CLOM) to 0, disabling clock output, then the pin is placed in the normal mode to function as a normal port.

  • Page 35: Int2

    INT0 has a noise eliminator. Two different sampling clocks for noise elimination can be switched. The acceptable width of a signal depends on the CPU clock. INT1 is an asynchronous input, and can accept a signal with some high level width regardless of what the CPU clock is.

  • Page 36: Xt1, Xt2

    µPD750008 USER'S MANUAL 2.2.14 XT1, XT2 These pins are used for connection to a crystal for subsystem clock oscillation. An external clock can also be applied. (a) Crystal oscillation Crystal 2.2.15 RESET This is the pin for active-low reset input. The RESET input is asynchronous.

  • Page 37: Ic (For The Μpd750004, Μpd750006, And Μpd750008 Only)

    2.2.18 IC (for the µPD750004, µPD750006, and µPD750008 only) The internally connected (IC) pin is used to set the µPD750008 to test mode for inspection prior to shipping. In normal operation, connect the IC pin to the V When the wiring between the IC pin and the V difference may occur between the IC pin and the V •...

  • Page 38: Pin Input/Output Circuits

    µPD750008 USER'S MANUAL 2.3 PIN INPUT/OUTPUT CIRCUITS Figure 2-1 shows schematic diagrams of the I/O circuitry of the µPD750008. Type A CMOS input buffer Type B Schmitt trigger input with hysteresis Figure 2-1. Pin Input/Output Circuits (1/2) Type B-C P-ch N-ch Type D Output...
  • Page 39 Figure 2-1. Pin Input/Output Circuits (2/2) Type E-B P.U.R. enable Data Type D Output disable Type A P.U.R.: Pull-Up Resistor Type F-A P.U.R. enable Data Type D Output disable Type B P.U.R.: Pull-Up Resistor Type F-B P.U.R. enable Output disable (P-ch) Data Output...

  • Page 40: Connection Of Unused Pins

    µPD750008 USER'S MANUAL 2.4 CONNECTION OF UNUSED PINS Pin name P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0-P12/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PCL P23/BUZ P30(/MD0)-P33(/MD3) P40-P43 P50-P53 P60-P63 P70-P73 P80-P81 Note IC (V Note ( ): µPD75P0016 Table 2-3. Connection of Unused Pins Recommended connection To be connected to V To be connected to V To be connected to V...

  • Page 41: Chapter 3 Features Of The Architecture And Memory Map

    CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP The 75XL series architecture of the µPD750008 has the following features: • Internal RAM of up to 4K words x 4 bits (12-bit address) •...
  • Page 42 µPD750008 USER'S MANUAL Applicable program processing MBE = 0 mode • Interrupt processing • Processing that repeats internal hardware and static RAM operations • Subroutine processing MBE = 1 mode • Usual program processing Figure 3-1. Use of MBE = 0 Mode and MBE = 1 Mode SET1 MBE CLR1 MBE Internal hardware...

  • Page 43: Data Memory Addressing Modes

    3.1.2 Data Memory Addressing Modes With the architecture of the µPD750008, seven addressing modes summarized in Figures 3-2 and 3-3, and Table 3-1 are available to address data memory space efficiently for each bit length of data to be processed. These addressing modes enable more efficient programming.

  • Page 44: Data Memory Organization And Addressing Range Of Each Addressing Mode

    µPD750008 USER'S MANUAL Figure 3-2. Data Memory Organization and Addressing Range of Each Addressing Mode Addressing mode Memory bank enable flag 000H 01FH 020H 07FH Data area Static RAM (memory bank 0) 0FFH 100H Data area Static RAM (memory bank 1) 1FFH Not provided F80H...

  • Page 45: Addressing Modes

    Representation Addressing mode format 1-bit direct mem.bit addressing 4-bit direct addressing 8-bit direct addressing 4-bit register indirect @HL+ addressing @HL– 8-bit register indirect addressing fmem.bit manipulation addressing pmem.@L @H+mem.bit Stack addressing — CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Table 3-1.
  • Page 46 µPD750008 USER'S MANUAL (2) 4-bit direct addressing (mem) In this addressing mode, the operand of an instruction directly specifies any area in the data memory space in units of four bits. As with the 1-bit direct addressing mode, in the MBE = 0 mode, a fixed space consisting of the static RAM area ranging from 000H to 07FH and the peripheral hardware area ranging from F80H to FFFH can be addressed.
  • Page 47 Example 2. Eight-bit data is latched into the serial interface shift register (SIO), and the transfer data is set at the same time. (4) 4-bit register indirect addressing (@rpa) In this addressing mode, the pointer (general register pair) specified in the operand of an instruction indirectly specifies a data memory space in units of four bits.

  • Page 48: Updating Static Ram Addresses

    µPD750008 USER'S MANUAL Example 2. The data memory of 00H to FFH is cleared to 0. LOOP: x 0H 0 x H DECS D DECS L 4-bit transfer INCS D DECS H Automatic decrement 4-bit manipulation DECS L 8-bit DECS HL manipulation INCS H F x H...
  • Page 49 (5) 8-bit register indirect addressing (@HL) In this addressing mode, the data pointer (HL register pair) indirectly specifies any area in the data memory space in units of eight bits. The 4-bit data at the address determined with bit 0 of the data pointer (bit 0 of the L register) set to 0 and the 4-bit data at the address incremented by 1 are processed as a pair on an 8-bit basis with the 8-bit accumulator (XA register pair).
  • Page 50 µPD750008 USER'S MANUAL (a) Specific address bit direct addressing (fmem.bit) In this addressing mode, peripheral equipment that frequently performs bit manipulations involving, for example, I/O ports and interrupt flags, can be processed at all times regardless of memory bank setting. Accordingly, the data memory addresses that allow this addressing mode to be used are FF0H to FFFH where I/O ports are mapped, and FB0H to FBFH where interrupt-related hardware is mapped.
  • Page 51 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP (b) Specific address bit register indirect addressing (pmem.@L) In this addressing mode, the bits of peripheral hardware I/O ports are indirectly specified using a register to allow continuous manipulations. This addressing mode can be applied to data memory addresses FC0H to FFFH.
  • Page 52 µPD750008 USER'S MANUAL (c) Specific 1-bit direct addressing (@H+mem.bit) This addressing mode enables any bit in the data memory space to be manipulated. In this addressing mode, the high-order four bits of the data memory address in the memory bank specified by MB = MBE·MBS are indirectly specified using the H register, and the low-order four bits and bit address are directly specified in the operand.
  • Page 53 (7) Stack addressing This addressing mode is used for save/restoration operation in interrupt processing or subroutine processing. In this addressing mode, the address indicated by the stack pointer (8 bits) of data memory bank 0 is specified. This addressing mode can be used for register save/restoration operation using the PUSH or POP instruction as well as save/restoration operation in interrupt and subroutine processing.

  • Page 54: General Register Bank Configuration

    µPD750008 USER'S MANUAL 3.2 GENERAL REGISTER BANK CONFIGURATION The µPD750008 contains four register banks, each consisting of eight general registers: X, A, B, C, D, E, H, and L. These registers are mapped to addresses 00H to 1FH in memory bank 0 of the data memory (see Figure 3-5).

  • Page 55: Example Of Register Bank Selection

    Figure 3-4. Example of Register Bank Selection <Main program> SET1 RBE SEL RB2 RB = 2 The setting of the RBS can be modified for subroutine processing or interrupt processing by saving or restoring the RBS with the PUSH or POP instruction. The RBE is set using the SET1 or CLR1 instruction.
  • Page 56 µPD750008 USER'S MANUAL (2) When used as an 8-bit register When the general register area is used on an 8-bit basis, the register pairs in the register bank specified by RBE·RBS can be specified as XA, BC, DE, and HL as shown in Figure 3-6, and the register pairs in the register bank that has the inverted value of bit 0 of the register bank (RB) can be specified as XA’, BC’, DE’, and HL’, thus providing up to eight 8-bit registers.

  • Page 57: General Register Configuration (4-Bit Processing)

    CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Figure 3-5. General Register Configuration (4-bit Processing) Register bank 0 (RBE·RBS = 0) Register bank 1 (RBE·RBS = 1) Register bank 2 (RBE·RBS = 2) Register bank 3 (RBE·RBS = 3)

  • Page 58: General Register Configuration (8-Bit Processing)

    µPD750008 USER'S MANUAL Figure 3-6. General Register Configuration (8-bit Processing) XA’ HL’ DE’ BC’ XA’ HL’ DE’ BC’ When RBE·RBS When RBE·RBS XA’ HL’ DE’ BC’ When RBE·RBS XA’ HL’ DE’ BC’ When RBE·RBS...

  • Page 59: Memory-Mapped I/O

    3.3 MEMORY-MAPPED I/O The µPD750008 employs memory-mapped I/O, which maps peripheral hardware such as timers and I/O ports to addresses F80H to FFFH in data memory space as shown in Figure 3-2. This means that there is no particular instruction to control peripheral hardware, but all peripheral hardware is controlled using memory manipulation instructions.

  • Page 60: Μpd750008 I/O Map

    µPD750008 USER'S MANUAL Hardware name (symbol) Address F80H Stack pointer (SP) Register bank selection register (RBS) F82H Bank selection register (BS) F83H Memory bank selection register (MBS) F84H Stack bank selection register (SBS) Basic interval timer mode register (BTM) F85H F86H Basic interval timer (BT) Note 2...
  • Page 61 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Hardware name (symbol) Address FA0H Timer/event counter mode register (TM0) Note 1 FA2H TOE0 FA4H Timer/event counter count register (T0) FA6H Timer/event counter modulo register (TMOD0) FA8H Timer counter mode register (TM1) Note 2 FAAH TOE1...
  • Page 62 µPD750008 USER'S MANUAL Hardware name (symbol) Address IST1 IST0 FB0H Program status word (PSW) FB2H Interrupt priority select register (IPS) FB3H Processor clock control register (PCC) FB4H INT0 edge detection mode register (IM0) FB5H INT1 edge detection mode register (IM1) FB6H INT2 edge detection mode register (IM2) FB7H...

  • Page 63: Chapter 3 Features Of The Architecture And Memory Map

    CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Hardware name (symbol) Address FD0H Clock output mode register (CLOM) FDCH Pull-up resistor specification register group A (POGA) FDEH Pull-up resistor specification register group B (POGB) FE0H Serial operation mode register (CSIM) CSIE CMDD RELD...
  • Page 64 µPD750008 USER'S MANUAL Hardware name (symbol) Address FF0H Port 0 (PORT0) FF1H Port 1 (PORT1) FF2H Port 2 (PORT2) FF3H Port 3 (PORT3) FF4H Port 4 (PORT4) FF5H Port 5 (PORT5) Note 2 FF6H Port 6 (PORT6) Note 2 FF7H Port 7 (PORT7) FF8H Port 8...

  • Page 65: Chapter 4 Internal Cpu Functions

    CHAPTER 4 INTERNAL CPU FUNCTIONS 4.1 Mk I MODE/Mk II MODE SWITCH FUNCTIONS 4.1.1 Differences between Mk I Mode and Mk II Mode The CPU of the µPD750008 subseries has two modes (Mk I mode and Mk II mode) and which mode is used is selectable.

  • Page 66: Setting Of The Stack Bank Selection Register (Sbs)

    µPD750008 USER'S MANUAL 4.1.2 Setting of the Stack Bank Selection Register (SBS) The Mk I mode and Mk II mode are switched by stack bank selection register. Figure 4-1 shows the register configuration. The stack bank selection register is set with a 4-bit memory operation instruction. To use the CPU in Mk I mode, initialize the register to 10xxB Note initialize it to 00xxB...

  • Page 67: Program Counter (Pc)

    The program counter is a binary counter which retains the address data of the program memory. The program counter consists of 12 bits in the µPD750004 (see Figure 4-2(a)), 13 bits in the µPD750006 and µPD750008 (see Figure 4-2(b)), and 14 bits in the µPD75P0016 (see Figure 4-2(c)).

  • Page 68: Program Memory (Rom)

    The program memory is used for storing programs, an interrupt vector table, GETI instruction reference table, table data, and so forth. The µPD750004, µPD750006, and µPD750008 are provided with a mask- programmable ROM as the program memory, and the µPD75P0016 is provided with a one-time PROM.

  • Page 69: Program Memory Map (In Μpd750004)

    Figure 4-3. Program Memory Map (in µPD750004) 0000H Internal reset start address Internal reset start address 0002H INTBT/INT4 start address INTBT/INT4 start address 0004H INT0 start address INT0 start address 0006H INT1 start address INT1 start address 0008H INTCSI start address...

  • Page 70: Program Memory Map (In Μpd750006)

    µPD750008 USER'S MANUAL Figure 4-4. Program Memory Map (in µPD750006) 0000H Internal reset start address Internal reset start address 0002H INTBT/INT4 start address INTBT/INT4 start address 0004H INT0 start address INT0 start address 0006H INT1 start address INT1 start address 0008H INTCSI start address INTCSI start address...

  • Page 71: Program Memory Map (In Μpd750008)

    Figure 4-5. Program Memory Map (in µPD750008) 0000H Internal reset start address Internal reset start address 0002H INTBT/INT4 start address INTBT/INT4 start address 0004H INT0 start address INT0 start address 0006H INT1 start address INT1 start address 0008H INTCSI start address INTCSI start address 000AH INTT0 start address...

  • Page 72: Program Memory Map (In Μpd75P0016)

    µPD750008 USER'S MANUAL Figure 4-6. Program Memory Map (in µPD75P0016) 0000H Internal reset start address Internal reset start address 0002H INTBT/INT4 start address INTBT/INT4 start address 0004H INT0 start address INT0 start address 0006H INT1 start address INT1 start address 0008H INTCSI start address INTCSI start address...

  • Page 73: Data Memory (Ram)

    4.4 DATA MEMORY (RAM): 512 WORDS x 4 BITS The data memory consists of a data area and peripheral hardware area as shown in Figure 4-7. The data memory consists of the following memory banks with each bank made of 256 words x 4 bits. •...

  • Page 74: Specification Of A Data Memory Bank

    µPD750008 USER'S MANUAL 4.4.2 Specification of a Data Memory Bank If the memory bank enable flag (MBE) enables bank specification (MBE = 1), a memory bank is specified with the 4-bit memory bank select register (MBS = 0, 1, 15). If the MBE disables bank specification (MBE = 0), memory bank 0 or 15 is automatically selected according to the addressing mode.
  • Page 75 Data memory is undefined when it is reset. For this reason, it is to be initialized to zero (RAM clear) usually at the start of a program. Remember to perform this initialization. Otherwise, unexpected bugs may occur. Example The following program clears data at addresses 000H to 1FFH in RAM. SET1 RAMC0: INCS...

  • Page 76: General Register

    µPD750008 USER'S MANUAL 4.5 GENERAL REGISTER: 8 x 4 BITS x 4 BANKS The general registers are mapped to particular addresses in data memory. Four banks of registers are provided, with each bank consisting of eight 4-bit registers (B, C, D, E, H, L, X, and A). The register bank (RB) to be enabled at the time of instruction execution is determined by: RB = RBE·RBS: (RBS = 0 to 3) Each general register allows 4-bit manipulation.

  • Page 77: Register Pair Format

    4.6 ACCUMULATOR In the µPD750008, the A register and XA register pair function as accumulators. The A register is mainly used for 4-bit data processing instructions, and the XA register pair is mainly used for 8-bit data processing instructions. For a bit manipulation instruction, the carry flag (CY) functions as a bit accumulator. Figure 4-9.

  • Page 78: Stack Pointer (Sp) And Stack Bank Select Register (Sbs)

    µPD750008 USER'S MANUAL 4.7 STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) The µPD750008 uses static RAM as stack memory (LIFO scheme), and the 8-bit register holding the start address of the stack area is the stack pointer (SP). The stack area is located at addresses 000H to 1FFH in memory banks 0 and 1.

  • Page 79: Format Of Stack Pointer And Stack Bank Select Register

    SP – 2 Lower bits of pair register SP – 1 Upper bits of pair register Note PC12 and PC13 are 0 in the µPD750004. PC13 is 0 in the µPD750006 and µPD750008. CHAPTER 4 INTERNAL CPU FUNCTIONS Note SBS3...

  • Page 80: Data Restored From The Stack Memory (Mk I Mode)

    SP – 1 Upper bits of pair register Notes 1. PC12 and PC13 are 0 in the µPD750004. PC13 is 0 in the µPD750006 and µPD750008. 2. PSW bits other than MBE and RBE are not saved or restored. Remark * indicates an undefined bit.

  • Page 81: Data Restored From The Stack Memory (Mk Ii Mode)

    Upper bits of pair register SP + 2 Notes 1. PC12 and PC13 are 0 in the µPD750004. PC13 is 0 in the µPD750006 and µPD750008. 2. PSW bits other than MBE and RBE are not saved or restored. Remark * indicates an undefined bit.

  • Page 82: Program Status Word (Psw)

    µPD750008 USER'S MANUAL 4.8 PROGRAM STATUS WORD (PSW): 8 BITS The program status word (PSW) consists of various flags closely associated with processor operations. The PSW is mapped to addresses FB0H and FB1H in data memory space. Four bits at address FB0H can be manipulated with a memory manipulation instruction.

  • Page 83: Carry Flag Manipulation Instructions

    Table 4-4. Carry Flag Manipulation Instructions Instruction dedicated to carry flag manipulation Bit transfer instruction Bit Boolean instruction Interrupt handling Remark mem*.bit represents the following bit addressing: • fmem.bit • pmem.@L • @H+mem.bit Example Bit 3 at address 3FH is ANDed with P33, then the result is set in P50. H,#3H MOV1 CY,@H+0FH.3...

  • Page 84: Information Indicated By The Interrupt Status Flag

    µPD750008 USER'S MANUAL Table 4-5. Information Indicated by the Interrupt Status Flag IST1 IST0 Status of processing Status 0 Status 1 Status 2 The interrupt priority control circuit (Figure 6-1) checks this flag to control multiple interrupts. The contents of the IST1 and IST0 are saved as part of the PSW to stack memory if an interrupt is accepted, then are automatically set to a one-step higher status.

  • Page 85: Bank Select Register (Bs)

    When the RBE is reset to 0, register bank 0 is always selected as general registers, regardless of the setting of the RBS. A RESET signal automatically initializes the RBE by setting the RBE to the state of bit 6 at program memory address 0.

  • Page 86: Register Bank To Be Selected With The Rbe And Rbs

    µPD750008 USER'S MANUAL Table 4-6. Register Bank to Be Selected with the RBE and RBS x: Don’t care Register bank Bank 0 is always selected. Bank 0 is selected. Bank 1 is selected. Bank 2 is selected. Bank 3 is selected. Always 0...

  • Page 87: Chapter 5 Peripheral Hardware Functions

    CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS DIGITAL I/O PORTS The µPD750008 employs the memory mapped I/O method. Thus, all input/output ports are mapped on the data memory space. Figure 5-1. Data Memory Addresses of Digital Ports Address FF0H FF1H FF2H FF3H FF4H FF5H FF6H...

  • Page 88: Types, Features, And Configurations Of Digital I/O Ports

    µPD750008 USER'S MANUAL 5.1.1 Types, Features, and Configurations of Digital I/O Ports Table 5-1 lists the types of digital I/O ports. Figures 5-2 to 5-6 show the configurations of the ports. Port name Function (symbol) PORT0 4-bit I/O PORT1 PORT3 Note 1 4-bit I/O PORT6...

  • Page 89: Configurations Of Ports 0 And 1

    Figure 5-2. Configurations of Ports 0 and 1 Selector CSIM Input buffer Input buffer INT2 INT1 INT0 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Internal INT4 output latch Selector Bit 0 of POGA Output buffer which can N-ch be switched to either open drain push-pull output or N-ch open-drain output...

  • Page 90: Configurations Of Ports 2 And 7

    µPD750008 USER'S MANUAL Input buffer Output Bits 2 and 7 of port mode register group B (m = 2, 7) Note For port 7 only Figure 5-3. Configurations of Ports 2 and 7 Bit m of POGA Key interrupt PMm = 0 PMm = 1 latch Output buffer...

  • Page 91: Configurations Of Ports 3N And 6N (N = 0 To 3)

    Figure 5-4. Configurations of Ports 3n and 6n (n = 0 to 3) Input buffer Output latch PMmn Corresponding bits of port mode register group A Note For port 6n only CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Note Key interrupt Input buffer with Note hysteresis PMmn = 0...

  • Page 92: Configurations Of Ports 4 And 5

    µPD750008 USER'S MANUAL Figure 5-5. Configurations of Ports 4 and 5 Pull-up resistor (Mask option) Input buffer PMm = 0 PMm = 1 Output latch N-ch open-drain output buffer Corresponding bits of port mode register group B (m = 4, 5)

  • Page 93: Configuration Of Port 8

    CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-6. Configuration of Port 8 Bit 0 of POGB Input buffer PM8 = 0 PM8 = 1 Ouput latch Corresponding bit of port mode register group C Pull-up resistor P-ch Output buffer...

  • Page 94: I/O Mode Setting

    µPD750008 USER'S MANUAL 5.1.2 I/O Mode Setting The I/O mode of each I/O port is set by the port mode register as shown in Figure 5-7. The I/O modes of ports 3 and 6 can be set bit by bit by port mode register group A (PMGA). The I/O modes of ports 2, 4, 5, and 7 can be set in units of four bits by port mode register group B (PMGB).

  • Page 95: Formats Of Port Mode Registers

    Figure 5-7. Formats of Port Mode Registers Port mode register group A Address FE8H PM63 PM62 PM61 PM60 PM33 Port mode register group B Address FECH — Port mode register group C Address FEEH — — — — CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Contents of specification Input mode (Output buffer off) Output mode (Output buffer on)

  • Page 96: Digital I/O Port Manipulation Instructions

    µPD750008 USER'S MANUAL 5.1.3 Digital I/O Port Manipulation Instructions All I/O ports contained in the µPD750008 are mapped to data memory space, so that all data memory manipulation instructions can be used. Table 5-3 lists the instructions that are particularly useful for I/O pin manipulation and their application ranges.
  • Page 97 (3) 8-bit manipulation instructions The MOV, XCH, and SKE instructions as well as the IN and OUT instructions can be used for ports 4 and 5 that allow 8-bit manipulation. As with 4-bit manipulation, memory bank 15 must be selected in advance. Example The data contained in the BC register pair is output on the output port specified by 8-bit data applied to ports 4 and 5.

  • Page 98: I/O Pin Manipulation Instructions

    µPD750008 USER'S MANUAL PORT Instruction Note 1 A, PORTn XA, PORTn Note 1 Note 1 OUT PORTn, A Note 1 OUT PORTn, XA SET1 PORTn.bit SET1 PORTn.@L Note 2 CLR1 PORTn.bit Note 2 CLR1 PORTn.@L PORTn.bit Note 2 PORTn.@L PORTn.bit PORTn.@L Note 2 MOV1 CY, PORTn.bit...

  • Page 99: Digital I/O Port Operation

    5.1.4 Digital I/O Port Operation When a data memory manipulation instruction is executed for a digital I/O port, the operation of the port and pins depends on the I/O mode setting (Table 5-3). This is because data taken in on the internal bus is the data input from the pins in the input mode, or the output latch data in the output mode, as obvious from the configurations of I/O ports.

  • Page 100: Operations By I/O Port Manipulation Instructions

    µPD750008 USER'S MANUAL Table 5-3. Operations by I/O Port Manipulation Instructions Instruction <1> Pin data is tested. <1> MOV1 CY, <1> Pin data is transferred to CY. AND1 CY, <1> An operation is performed on pin data and <1> XOR1 CY, <1>...

  • Page 101: Specification Of Bilt-In Pull-Up Resistors

    5.1.5 Specification of Bilt-in Pull-Up Resistors A pull-up resistor can be contained at each port pin of the µPD750008 (except for P00). Whether to use the pull-up resistor can be specified by software (for some pins) or a mask option (for the other pins). Table 5-4 shows how a built-in pull-up resistor is specified for each port pin.

  • Page 102: I/O Timing Of Digital I/O Ports

    µPD750008 USER'S MANUAL Figure 5-8. Pull-Up Resistor Specification Register Format Pull-up resistor specification register group A Address FDCH Pull-up resistor specification register group B Address — FDEH 5.1.6 I/O Timing of Digital I/O Ports Figure 5-9 shows the timing of data output to an output latch and the timing of taking in pin data or output latch data on the internal bus.

  • Page 103: On Timing Chart Of Built-In Pull-Up Resistor Connected By Software

    Figure 5-9. I/O Timing Chart of Digital I/O Ports (2/2) (b) When data is input by a 2-machine cycle instruction Instruction execution Input timing (c) When data is latched by a 1-machine cycle instruction Instruction Manipulation instruction execution Output latch (output pin) (d) When data is latched by a 2-machine cycle instruction Instruction...

  • Page 104: Clock Generator

    µPD750008 USER'S MANUAL 5.2 CLOCK GENERATOR The clock generator supplies various clock signals to the CPU and peripheral hardware to control the CPU operation mode. 5.2.1 Clock Generator Configuration Figure 5-11 shows the configuration of the clock generator. Figure 5-11. Block Diagram of the Clock Generator Subsystem clock generator Main system...

  • Page 105: Functions And Operations Of The Clock Generator

    5.2.2 Functions and Operations of the Clock Generator The clock generator generates the following clocks, and controls the CPU operation modes such as the standby mode. • Main system clock f • Subsystem clock f • CPU clock F • Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register (PCC) and system clock control register (SCC).
  • Page 106 µPD750008 USER'S MANUAL (1) Processor clock control register (PCC) The PCC is a 4-bit register for selecting a CPU clock F with the low-order two bits and for controlling the CPU operation mode with the high-order two bits (see Figure 5-12). When bit 3 or bit 2 is set to 1, the standby mode is set.

  • Page 107: Format Of The Processor Clock Control Register

    Figure 5-12. Format of the Processor Clock Control Register Address FB3H PCC3 PCC2 PCC1 PCC0 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Symbol CPU clock selection bit (Operation with f = 6.0 MHz) SCC3, SCC0 = 00 ( ) is actual frequency at f = 6.0 MHz CPU clock frequency 1 machine cycle...

  • Page 108: Format Of The System Clock Control Register

    µPD750008 USER'S MANUAL (2) System clock control register (SCC) The SCC is a 4-bit register for selecting CPU clock F with the least significant bit and for controlling the termination of main system clock generation with the most significant bit (see Figure 5-13). Bits 0 and 3 of the SCC are located at the same data memory address, but both bits cannot be changed at the same time.

  • Page 109: External Circuit For The Main System Clock Oscillator

    (3) System clock oscillator The main system clock oscillator operates with a crystal resonator or ceramic resonator connected to the X1 and X2 pins. An external clock can also be input. Input the clock signal to the X1 pin and the reversed signal to the X2 pin.

  • Page 110: Examples Of Oscillator Connections Which Should Be Avoided

    µPD750008 USER'S MANUAL Any line carrying a high pulsating current must be kept away as far as possible. • The grounding point of the capacitor of the oscillator must have the same potential as that of V ing a high current. •...
  • Page 111 Figure 5-16. Examples of Oscillator Connections Which Should Be Avoided (2/2) (c) A high pulsating current is too close to the signal line. µPD750008 (e) A signal is taken directly from the resonator. µPD750008 Remark When wiring the subsystem clock, read X1 and X2 as XT1 and XT2 respectively. In this case, a resistor must be added to XT2 in series.

  • Page 112: Subsystem Clock Oscillator

    µPD750008 USER'S MANUAL (4) Frequency divider The frequency divider divides the output (f (5) Control functions of subsystem clock oscillator The subsystem clock oscillator of the µPD750008 subseries has two control functions to decrease the supply current. • The function to select with the software whether to use the built-in feedback resistor •...

  • Page 113: Sub-Oscillator Control Register (Sos) Format

    (6) Sub-oscillator control register (SOS) The SOS register specifies whether to use the built-in feedback register and controls the drive current of the built-in inverter. (See Figure 5-18.) Inputting a RESET signal clears all bits of the SOS register. The functions of each flag in the SOS register are described below.

  • Page 114: System Clock And Cpu Clock Setting

    µPD750008 USER'S MANUAL 5.2.3 System Clock and CPU Clock Setting (1) Time required to change the system clock and CPU clock The system clock and CPU clock can be changed by using the least significant bit of the SCC and the low-order two bits of the PCC.

  • Page 115: Changing The System Clock And Cpu Clock

    (2) Procedure for changing the system clock and CPU clock The procedure for changing the system clock and CPU clock is explained using Figure 5-19. Figure 5-19. Changing the System Clock and CPU Clock Commercial power line voltage pin voltage RESET signal System clock CPU clock...

  • Page 116: Clock Output Circuit

    µPD750008 USER'S MANUAL 5.2.4 Clock Output Circuit (1) Configuration of the clock output circuit Figure 5-20 shows the configuration of the clock output circuit. (2) Functions of the clock output circuit The clock output circuit outputs a clock pulse signal on the P22/PCL pin to output remote control signals or to supply clock pulses to a peripheral LSI device.

  • Page 117: Format Of The Clock Output Mode Register

    (3) Clock output mode register (CLOM) The CLOM is a 4-bit register to control clock output. The CLOM is set by a 4-bit memory manipulation instruction. No read operation is allowed on this register. CPU clock F is output on the PCL/P22 pin. Example MB15 A,#1000B...

  • Page 118: Application To Remote Control Output

    µPD750008 USER'S MANUAL (4) Application to remote control output The clock output function of the µPD750008 is applicable to remote control output. The frequency of the carrier for remote control output is selected by the clock frequency select bit of the clock output mode register.

  • Page 119: Basic Interval Timer/Watchdog Timer

    5.3 BASIC INTERVAL TIMER/WATCHDOG TIMER The µPD750008 contains an 8-bit basic interval timer/watchdog timer, which has the following functions: (a) Interval timer operation which generates a reference timer interrupt (b) Operation as a watchdog timer for detecting program crashes and resetting the CPU (c) Selection of a wait time for releasing the standby mode, and counting (d) Reading the count value 5.3.1 Configuration of the Basic Interval Timer/Watchdog Timer...

  • Page 120: Format Of The Basic Interval Timer Mode Register

    µPD750008 USER'S MANUAL When bit 3 is set to 1, the BT is cleared, and the basic interval ltimer/watchdog timer interrupt request flag (IRQBT) is also cleared (to start the basic interval timer/watchdog timer). A RESET signal clears the interval timer to 0, and the longest interrupt request signal generation interval time is set.

  • Page 121: Watchdog Timer Enable Flag (Wdtm)

    5.3.3 Watchdog Timer Enable Flag (WDTM) WDTM, when set, is a flag for enabling the generation of the reset signal when the basic interval timer overflows. WDTM is set by a bit manipulation instruction. It cannot be cleared by an instruction. Example Set the watchdog timer function.

  • Page 122: Operation Of The Watchdog Timer

    µPD750008 USER'S MANUAL 5.3.5 Operation of the Watchdog Timer When WDTM is set to 1, the basic interval timer/watchdog timer functions as a watchdog timer. An internal reset signal is generated when the basic interval timer (BT) overflows. No reset signal, however, is generated during the oscillation wait time following the STOP instruction has been released (WDTM cannot be cleared without using reset).

  • Page 123: Other Functions

    Module 1: SET1 SET1 Module 2: SET1 SET1 5.3.6 Other Functions The basic interval timer/watchdog has the following functions regardless of whether it operates as a basic interval timer or watchdog timer: <1> Selecting and counting the wait time after the standby mode is released <2>...
  • Page 124 µPD750008 USER'S MANUAL (2) Reading the count The count status of the basic interval timer (BT) can be read by using an 8-bit manipulation instruction. No data can be loaded to the timer. Caution When reading the count value of BT, execute a read instruction twice so that unstable data which has been counted will not be read.

  • Page 125: Clock Timer

    SET1 RETI 5.4 CLOCK TIMER The µPD750008 contains one clock timer, which has the following functions. (a) The clock timer sets the test flag (IRQW) every 0.5 seconds. The IRQW can release the standby mode. (b) Either the main system clock or the subsystem clock can be used to produce 0.5-second intervals. Use a main system clock of 4.194304 MHz.

  • Page 126: Configuration Of The Clock Timer

    µPD750008 USER'S MANUAL 5.4.1 Configuration of the Clock Timer Figure 5-26 shows the configuration of the clock timer. Figure 5-26. Block Diagram of the Clock Timer From the (32.768 kHz) Selector clock generator (32.768 kHz) The values in parentheses are for f 5.4.2 Clock Mode Register The clock mode register (WM) is an 8-bit register which controls the clock timer.

  • Page 127: Clock Mode Register Format

    Example Time is set using the main system clock (4.19 MHz), and buzzer output is enabled: CLR1 MBE XA, #84H WM, XA Figure 5-27. Clock Mode Register Format Address F98H Remark ( ) for f = 32.768 kHz CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS ;...

  • Page 128: Timer/Event Counter

    µPD750008 USER'S MANUAL 5.5 TIMER/EVENT COUNTER The µPD750008 has one timer/event counter channel (channel 0) and one timer counter channel (channel 1). Figures 5-28 and 5-29 show the configuration of these channels. In this section, the timer/event counter and timer counters are referred to as "timer/event counters." When you read this section for description of channel 1, take "timer/event counter"...
  • Page 129 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS...
  • Page 130 µPD750008 USER'S MANUAL...
  • Page 131 (1) Timer/event counter mode register (TM0, TM1) The mode register (TMn) is an 8-bit register which controls the timer/event counter. Its format is shown in Figures 5-30 and 5-31. The timer/event counter mode register is set by an 8-bit memory manipulation instruction. Bit 3 is a timer start bit and can be operated bit-wise.

  • Page 132: Timer/Event Counter Mode Register (Channel 0) Format

    µPD750008 USER'S MANUAL Figure 5-30. Timer/Event Counter Mode Register (Channel 0) Format Address FA0H TM06 TM05 TM04 TM03 TM02 Count pulse (CP) selection bit When f = 6.00 MHz TM06 TM05 TM04 TI0 rising edge TI0 falling edge (5.86 kHz) (23.4 kHz) (93.8 kHz) (375 kHz)

  • Page 133: Timer Counter Mode Register (Channel 1) Format

    Figure 5-31. Timer Counter Mode Register (Channel 1) Format Address FA8H TM16 TM15 TM14 Count pulse (CP) select bit When f = 6.00 MHz TM16 TM14 TM15 Other than above When f = 4.19 MHz TM16 TM15 TM14 Other than above Timer start indication bit TM13 When 1 is written into the bit, the counter and IRQT1 flag are cleared.

  • Page 134: 8-Bit Timer/Event Counter Mode Operation

    µPD750008 USER'S MANUAL (2) Timer/event counter output enable flag (TOE0, TOE1) The timer/event counter output enable flag (TOE0, TOE1) controls the output enable/disable to the PTO0 and PTO1 pins in the timer out flip-flop (TOUT flip-flop ) status. The timer out flip-flop is inverted by the match signal sent from the comparator. When bit 3 of the timer/ event counter mode register (TM0, TM1) is set to 1, the timer out flip-flop is cleared to 0.

  • Page 135: Timer/Event Counter Mode Register Setup

    Figure 5-33. Timer/Event Counter Mode Register Setup (1/2) (a) In the case of timer/event counter (channel 0) Address FA0H TM06 TM05 TM04 Count pulse (CP) selection bit TM06 TM05 TM04 Other than above Timer start indication bit TM03 When “1” is written into the bit, the counter and IRQT0 flag are cleared. If bit 2 is set to “1”, count operation is started.

  • Page 136: Timer/Event Counter Output Enable Flag Setup

    µPD750008 USER'S MANUAL Figure 5-33. Timer/Event Counter Mode Register Setup (2/2) Address FA8H Count pulse (CP) selection bit Timer start indication bit Operation mode (b) Timer/event counter output enable flag (TOEn) The TOEn is manipulated by a bit manipulation instruction. The TOEn is cleared to 0 by an internal reset signal.

  • Page 137: Resolution And Longest Setup Time

    (2) Timer/event counter time setting [Timer setup time] (cycle) is found by dividing [modulo register contents + 1] by [count pulse (CP) frequency] selected by setting the mode register. T (sec) = = (n + 1) · (resolution) T (sec) : Timer setup time (seconds) (Hz) : Count pulse frequency (Hz) : Modulo register content (n •...

  • Page 138: Configuration Of Timer/Event Counter

    µPD750008 USER'S MANUAL (3) Timer/event counter operation The timer/event counter operates as follows. Figure 5-35 shows the configuration of the timer/event counter. <1> The count pulse (CP) is selected by setting the mode register (TMn) and is input to the count register (Tn).

  • Page 139: Count Operation Timing

    Count pulse(CP) Modulo register (TMODn) Count register (Tn) Reset TOUT F/F Timer start indication (4) Applications of the timer/event counter (a) Timer/event counter is used as an interval timer that generates interrupts at intervals of 30 ms. • The high-order four bits of the mode register are set to 0100B to select maximum set time 43.7 ms (at f = 6.00 MHz).

  • Page 140: Notes On Timer/Event Counter Applications

    µPD750008 USER'S MANUAL <Sample program> MB15 XA,#100 – 1 TMOD0,XA XA,#00001100B TM0,XA IET0 5.5.3 Notes on Timer/Event Counter Applications (1) Time error at the start of the timer A maximum error of one count pulse (CP) cycle from a value calculated according to Section 5.5.2 (2) occurs in a time period from the start of the timer (bit 3 of the TM0 is set) to the generation of a match signal.
  • Page 141 (3) Error in reading the count register The contents of the count register can be read using an 8-bit data memory manipulation instruction at any time. During operation by such an instruction, all count pulse changes are held not to change the count register.
  • Page 142 µPD750008 USER'S MANUAL Clock A Clock B (5) Operation after the modulo register is changed The contents of the modulo register are changed when an 8-bit data memory manipulation instruction is executed. Modulo register Count register Match signal If the new value of the modulo register is less than the value of the count register, the count register continues count operation until it overflows, then it restarts count operation from 0.

  • Page 143: Serial Interface

    In this mode, communication with multiple devices can be performed using two lines: Serial clock (SCK) and serial data bus (SB0 or SB1). This mode conforms to the NEC serial bus format. In this mode, the transmitter can output, on the serial data bus, an address for selecting a device subject to serial communication, commands directed to the remote device, and data.

  • Page 144: Configuration Of Serial Interface

    µPD750008 USER'S MANUAL Figure 5-38. Example of the SBI System Configuration Master CPU SB0, SB1 5.6.2 Configuration of Serial Interface Figure 5-39 shows the block diagram of the serial interface. Serial clock SB0, SB1 Address Command Data SB0, SB1 Slave CPU Address 1 Slave IC Address N...
  • Page 145 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS BSYE ACKE ACKT...
  • Page 146 µPD750008 USER'S MANUAL (1) Serial operation mode register 0 (CSIM) CSIM is an 8-bit register which specifies a serial interface operation mode, serial clock, wake-up function, and so forth. (See (1) in Section 5.6.3 for details.) (2) Serial bus interface control register (SBIC) SBIC is an 8-bit register consisting of bits for controlling the serial bus and flags for indicating the states of input data from the serial bus.

  • Page 147: Register Functions

    (9) Serial clock control circuit The serial clock control circuit controls the serial clock to be supplied to the shift register, or controls the clock to be output to the SCK pin when the internal system clock is used. (10) Busy/acknowledge output circuit and bus release/command/acknowledge detection circuit The busy/acknowledge output circuit and bus release/command/acknowledge detection circuit output and detect control signals generated in the SBI mode.
  • Page 148 µPD750008 USER'S MANUAL Figure 5-40. Format of Serial Operation Mode Register (CSIM) (2/4) Serial interface operation enable/disable specification bit (W) Shift register operation CSIE Shift operation disabled Shift operation enabled Signal from address comparator (R) Note Condition for being cleared (COI = 0) When the data in the slave address register (SVA) does not match the data in the shift register...
  • Page 149 Figure 5-40. Format of Serial Operation Mode Register (CSIM) (3/4) Serial interface operation mode selection bit (W) Operation CSIM4 CSIM3 CSIM2 mode 3-wire serial I/O mode SBI mode 2-wire serial I/O mode Remark x: Don’t care Serial clock selection bit (W) CSIM1 CSIM0 3-wire serial I/O mode...
  • Page 150 µPD750008 USER'S MANUAL Figure 5-40. Format of Serial Operation Mode Register (CSIM) (4/4) Remarks 2. The P01/SCK pin assumes any of the following states according to the state of CSIE, CSIM1, and CSIM0: CSIE 3. When clearing CSIE during serial transfer, use the following procedure: <1>...

  • Page 151: Format Of Serial Bus Interface Control Register (Sbic)

    (2) Serial bus interface control register (SBIC) Figure 5-41 shows the format of the serial bus interface control register (SBIC). SBIC is an 8-bit register consisting of bits for controlling the serial bus and flags for indicating the states of input data from the serial bus. SBIC is used mainly in the SBI mode. SBIC is manipulated using a bit manipulation instruction.
  • Page 152 µPD750008 USER'S MANUAL Figure 5-41. Format of Serial Bus Interface Control Register (SBIC) (2/3) Busy enable bit (R/W) BSYE <1> The busy signal is automatically disabled. <2> Busy signal output is stopped in phase with the falling edge of SCK immediately after clear instruction execution.
  • Page 153 Figure 5-41. Format of Serial Bus Interface Control Register (SBIC) (3/3) Bus release detection flag (R) RELD Condition for being cleared (RELD = 0) <1> The transfer start instruction is executed. <2> The RESET signal is generated. <3> CSIE = 0 (Figure 5-40) <4>...

  • Page 154: Peripheral Hardware Of Shift Register

    µPD750008 USER'S MANUAL (3) Shift register (SIO) Figure 5-42 shows the configuration of peripheral hardware of shift register. SIO is an 8-bit register which performs parallel-serial conversion and serial transfer (shift) operation in phase with the serial clock. Serial transfer is started by writing data to SIO. In transmission, data written to SIO is output on the serial output (SO) or serial data bus (SB0 or SB1).

  • Page 155: Operation Halt Mode

    (a) Slave address detection [In the SBI mode] SVA is used when the µPD750008 is connected as a slave device to the serial bus. SVA is an 8- bit register for a slave to set its slave address (number assigned to it). The master outputs a slave address to the connected slaves to select a particular slave.
  • Page 156 µPD750008 USER'S MANUAL Address CSIE FE0H Note The status of the P01/SCK pin is selectable. Remark (R): Read only (W): Write only Serial interface operation enable/disable specification bit (W) Shift register operation CSIE0 Shift operation disabled Serial clock selection bit (W) The P01/SCK pin assumes the following state according to the setting of CSIM0 and CSIM1: When clearing CSIE during serial transfer, use the following procedure: <1>...

  • Page 157: Three-Wire Serial I/O Mode Operations

    5.6.5 Three-Wire Serial I/O Mode Operations The three-wire serial I/O mode is compatible with other modes used in the 75 XL series, 75X series, µPD7500 series, and 87AD series. Communication is performed using three lines: Serial clock (SCK), serial output (SO), and serial input (SI). Figure 5-43.
  • Page 158 µPD750008 USER'S MANUAL Serial interface operation enable/disable specification bit (W) Shift register operation CSIE Shift operation enabled Signal from address comparator (R) Note Condition for being cleared (COI = 0) When the slave address register (SVA) does not match the data of the shift register Note COI can be read only before serial transfer is started or after serial transfer is completed.
  • Page 159 (b) Serial bus interface control register (SBIC) To use the three-wire serial I/O mode, set SBIC as shown below. (For details on SBIC format, see (2) in Section 5.6.3.) SBIC is manipulated using a bit memory manipulation instruction. When the RESET signal is input, SBIC is set to 00H. In the figure below, hatched portions indicate the bits used in the three-wire serial I/O mode.

  • Page 160: Timing Of Three-Wire Serial I/O Mode

    µPD750008 USER'S MANUAL Figure 5-44. Timing of Three-Wire Serial I/O Mode IRQCSI Execution of instruction that writes data to SIO (Transfer start request) The SO pin becomes a CMOS output and outputs the state of the SO latch. So the output state of the SO pin can be manipulated by setting the RELT bit and CMDT bit.

  • Page 161: Operations Of Relt And Cmdt

    (4) Signals Figure 5-45 shows operations of RELT and CMDT. SO latch RELT CMDT (5) Switching between MSB and LSB as the first transfer bit The three-wire serial I/O mode has a function that can switch between the MSB and LSB as the first bit of transfer.
  • Page 162 µPD750008 USER'S MANUAL (6) Transfer start Serial transfer is started by writing transfer data into shift register (SIO), provided that the following two conditions are satisfied: • The serial interface operation enable/disable specification bit (CSIE) is set to 1. • The internal serial clock is not operating after 8-bit serial transfer, or SCK is high. Caution Setting CSIE after writing data to the shift register does not start transfer.
  • Page 163 (b) Data is transmitted and received starting with the LSB on an external clock (slave operation). (In this case, the function of inverting the MSB/LSB is used for shift register read/write operation.) <Sample program> Main routine CLR1 XA,#84H CSIM,XA XA,TDATA SIO,XA IECSI Interrupt routine (MBE = 0)

  • Page 164: Two-Wire Serial I/O Mode

    µPD750008 USER'S MANUAL <Sample program> (master side): CLR1 LOOP : SKTCLR 5.6.6 Two-Wire Serial I/O Mode The two-wire serial I/O mode can be made compatible with any communication format by programming. In this mode, communication is basically performed using two lines: Serial clock (SCK) and serial data input/ output (SB0 or SB1).
  • Page 165 (a) Serial operation mode register (CSIM) To use the two-wire serial I/O mode, set CSIM as shown below. (For details on CSIM format, see (1) in Section 5.6.3.) CSIM is manipulated using an 8-bit manipulation instruction. Bits 7, 6, and 5 of CSIM can be manipulated bit by bit.
  • Page 166 µPD750008 USER'S MANUAL Serial interface operation mode selection bit (W) CSIM4 CSIM3 CSIM2 Serial clock selection bit (W) CSIM1 CSIM0 External clock applied to SCK pin Timer/event counter output (TOUT0) (65.5 kHz) Remark The value at 4.19 MHz is indicated in parentheses. (b) Serial bus interface control register (SBIC) To use the two-wire serial I/O mode, set SBIC as shown below.

  • Page 167: Timing Of Two-Wire Serial I/O Mode

    Bus release trigger bit (W) RELT Control bit for bus release signal (REL) trigger output. By setting RELT = 1, the SO latch is set to 1. Then the RELT bit automatically cleared to 0. Caution Never use bits other than RELT and CMDT in the two-wire serial I/O mode. (2) Communication operation The two-wire serial I/O mode transfers data, with eight bits as one block.

  • Page 168: Serial Clock Selection And Application (In The Two-Wire Serial I/O Mode)

    µPD750008 USER'S MANUAL (3) Serial clock selection To select the serial clock, manipulate bits 0 and 1 of serial operation mode register (CSIM). The serial clock can be selected out of the following four clocks: Table 5-8. Serial Clock Selection and Application (In the Two-Wire Serial I/O Mode) Mode register Serial clock CSIM...
  • Page 169 (6) Error detection In the two-wire serial I/O mode, the state of serial bus SB0 or SB1 being used for communication is loaded into the shift register (SIO) of the transmitting device. So a transmission error can be detected by the methods described below.

  • Page 170: Sbi Mode Operation

    5.6.7 SBI Mode Operation The SBI (serial bus interface) is a high-speed serial interface that conforms to the NEC serial bus format. To allow communication with multiple devices on a single-master and high-speed serial bus using two signal lines, the SBI has a bus configuration function added to the clock synchronous serial I/O method.
  • Page 171 Cautions 1. In the SBI mode, the serial data bus pin SB0 (or SB1) is an open-drain output. So the serial data bus line is placed in the wired OR state. A pull-up resistor is required for the serial data bus line. 2.

  • Page 172: Timing Of Sbi Transfer

    µPD750008 USER'S MANUAL (2) SBI definition The format of serial data and signal used in the SBI mode are described below. Serial data to be transferred in the SBI mode is classified into three types: Address, command, and data. Serial data forms one frame as shown below. Figure 5-51 is a timing chart for transferring address, command, and data.

  • Page 173: Bus Release Signal

    (a) Bus release signal (REL) When the SCK line is high (the serial clock is not output), the SB0 (or SB1) line changes from low to high. This signal is called the bus release signal, and is output by the master. This signal indicates that the master is to send an address to a slave.

  • Page 174: Slave Selection Using An Address

    µPD750008 USER'S MANUAL Figure 5-55. Slave Selection Using an Address Transmits address for slave 2 (d) Command and data The master sends commands to the slave selected by sending an address. The master also transfers data to or from the slave. SB0, SB1 SB0, SB1 The 8-bit data following the command signal is defined as a command.

  • Page 175: Acknowledge Signal

    CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5-58. Acknowledge Signal [When output in phase with the 11th clock of SCK] SB0, SB1 [When output in phase with the 9th clock of SCK] SB0, SB1 The acknowledge signal is a one-shot pulse output in phase with the falling edge of SCK after 8-bit data transfer.

  • Page 176: Busy And Ready Signals

    µPD750008 USER'S MANUAL (f) Busy signal (BUSY) and ready signal (READY) The busy signal informs the master that a slave is getting ready for data transfer. The ready signal informs the master that a slave is ready for data transfer. In the SBI mode, a slave notifies the master of the busy state by changing SB0 (or SB1) from high to low.
  • Page 177 Serial interface operation enable/disable specification bit (W) Shift register operation CSIE Shift operation enabled Signal from address comparator (R) Note Condition for being cleared (COI = 0) When the slave address register (SVA) does not match the data of the shift register Note COI can be read only before serial transfer is started or after serial transfer is completed.
  • Page 178 µPD750008 USER'S MANUAL Serial clock selection bit (W) CSIM1 CSIM0 External clock applied to SCK pin Timer/event counter output (TOUT0) (262 kHz) (524 kHz) Remark The value at 4.19 MHz is indicated in parentheses. (b) Serial bus interface control register (SBIC) To use the SBI mode, set SBIC as shown below.
  • Page 179 Acknowledge detection flag (R) ACKD Condition for being cleared (ACKD = 0) <1> The transfer operation is started. <2> The RESET signal is entered. Acknowledge enable bit (R/W) ACKE Disables automatic output of the acknowledge signal. (Output by ACKT is possible.) When set before transfer When set after transfer Acknowledge trigger bit (W)

  • Page 180: Serial Clock Selection And Application (In The Sbi Mode)

    µPD750008 USER'S MANUAL Bus release trigger bit (W) RELT Control bit for bus release signal (REL) trigger output. By setting RELT = 1, the SO latch is set to 1. Then the RELT bit automatically cleared to 0. Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or after serial transfer.

  • Page 181: Operations Of Relt, Cmdt, Reld, And Cmdd (Slave)

    Figure 5-60. Operations of RELT, CMDT, RELD, and CMDD (Master) "H" SO latch RELT CMDT RELD CMDD Figure 5-61. Operations of RELT, CMDT, RELD, and CMDD (Slave) Transfer start request SO latch RELT (Master) CMDT (Master) RELD CMDD CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS When address match is found When address mismatch is found Transfer start request...

  • Page 182: Operation Of Ackt

    µPD750008 USER'S MANUAL When ACKT is set after transfer completion SB0, SB1 ACKT Caution Do not set the ACKT until the transfer is completed. (a) When ACKE = 1 at time of transfer completion SB0, SB1 ACKE (b) When ACKE is set after transfer completion SB0, SB1 ACKE (c) When ACKE = 0 at time of transfer completion...

  • Page 183: Operation Of Ackd

    Figure 5-63. Operation of ACKE (2/2) (d) When ACKE = 1 period is too short SB0, SB1 ACKE Figure 5-64. Operation of ACKD (1/2) (a) When ACK signal is output during the ninth SCK clock SB0, SB1 ACKD (b) When ACK signal is output after the ninth SCK clock SB0, SB1 ACKD CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS...

  • Page 184: Operation Of Bsye

    µPD750008 USER'S MANUAL (c) Clear timing for case where start of transfer is directed during BUSY SB0, SB1 ACKD SB0, SB1 BSYE Figure 5-64. Operation of ACKD (2/2) Figure 5-65. Operation of BSYE When BSYE = 1 at this point Transfer start request Transfer start BUSY...
  • Page 185 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS...
  • Page 186 µPD750008 USER'S MANUAL...

  • Page 187: Pin Configuration

    (6) Pin configuration The configurations of serial clock pin SCK and serial data bus pin (SB0 or SB1) are as follows: (a) SCK: Pin for serial clock I/O <1> Master : CMOS, push-pull output <2> Slave : Schmitt input (b) SB0, SB1: Pin for serial data I/O Output to SB0 or SB1 is an N-ch open-drain output and input is Schmitt input for both the master and a slave.
  • Page 188 µPD750008 USER'S MANUAL (7) Address match detection method In the SBI mode, communication starts when the master selects a particular slave device by outputting an address. An address match is detected by hardware. The slave address register (SVA) is available. In the wake- up state (WUP = 1), IRQCSI is set only when the address transmitted by the master and the value held in SVA match.
  • Page 189 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS...
  • Page 190 µPD750008 USER'S MANUAL...
  • Page 191 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS...
  • Page 192 µPD750008 USER'S MANUAL...
  • Page 193 (10) Transfer start Serial transfer is started by writing transfer data in shift register (SIO), provided that the following two conditions are satisfied: • The serial interface operation enable/disable bit (CSIE) is set to 1. • The internal serial clock is not operating after 8-bit serial transfer, or SCK is high. Cautions 1.

  • Page 194: Example Of Serial Bus Configuration

    µPD750008 USER'S MANUAL (12) SBI mode This section describes an example of application which performs serial data communication in the SBI mode. In the example, the µPD750008 can be used as either the master CPU or a slave CPU on the serial bus.

  • Page 195: Transfer Format Of The Read Command

    (b) Explanation of commands (i) Types of commands This example uses the following commands: <1> READ command <2> WRITE command <3> END command <4> STOP command <5> STATUS command : Reads slave status. <6> RESET command : Sets currently selected slave as non-selected slave. <7>...

  • Page 196: Transfer Format Of The Write And End Commands

    µPD750008 USER'S MANUAL When the slave receives a transmission data count, if it has data enough for transmitting the specified number of bytes of data, the slave returns ACK. If the slave does not have enough data for transmission, an error occurs; ACK is not returned in this case. The master sends ACK to the slave each time it receives one byte.

  • Page 197: Transfer Format Of The Status Command

    <3> STATUS command The STATUS command reads the status of the current slave. Figure 5-75. Transfer Format of the STATUS Command STATUS Data Remark M: Output by the master S: Output by the slave The slave returns the status in the format shown in Figure 5-78. Figure 5-76.

  • Page 198: Transfer Format Of The Reset Command

    µPD750008 USER'S MANUAL <4> RESET command The RESET command changes the currently selected slave to a non-selected slave. When a RESET command is transmitted, any slave can be placed in the non-selected state. Figure 5-77. Transfer Format of the RESET Command Remark M: Output by the master S: Output by the slave <5>...

  • Page 199: Manipulation Of Sck Pin Output

    If ACK is not returned from the slave within a predetermined period after transmission completion, the occurrence of an error is assumed; the master outputs the ACK signal as a dummy. Figure 5-79. Master and Slave Operation in Case of Error Processing by slave SB0, SB1 Erroneous data...

  • Page 200: Sck/P01 Pin Circuit Configuration

    µPD750008 USER'S MANUAL Example To output one SCK/P01 pin clock cycle by software MB15 XA,#10000011B CSIM,XA CLR1 0FF0H.1 SET1 0FF0H.1 Figure 5-80. SCK/P01 Pin Circuit Configuration P01/SCK The P01 output latch is mapped to bit 1 of address FF0H. A RESET signal sets the P01 output latch to Cautions 1.

  • Page 201: Bit Sequential Buffer

    5.7 BIT SEQUENTIAL BUFFER: 16-BIT The bit sequential buffer (BSB) is special data memory for bit manipulations. In particular, the buffer allows bit manipulations to be performed very easily by sequentially changing address and bit specifications. So the buffer is useful in processing long data bit by bit. This data memory consists of 16 bits, and allows pmem.@L addressing with a bit manipulation instruction.
  • Page 202 µPD750008 USER'S MANUAL Example To output 16-bit data of BUFF1 and BUFF2 serially from bit 0 of port 3: CLR1 LOOP0: SET1 LOOP1: CLR1 LOOP2: INCS XA,BUFF1 BSB0,XA ; Set BSB0 and BSB1 XA,BUFF2 BSB2,XA ; Set BSB2 and BSB3 L,#0 BSB0, @L ;...

  • Page 203: Chapter 6 Interrupt And Test Functions

    CHAPTER 6 INTERRUPT AND TEST FUNCTIONS The µPD750008 has seven vectored interrupt sources and two test inputs, allowing a wide range of applications. In addition, the interrupt control circuitry of the µPD750008 has the following features for very high-speed interrupt processing. (1) Interrupt functions (a) Hardware controlled vectored interrupt function which can control whether or not to accept an interrupt using the interrupt flag (IExxx) and interrupt master enable flag (IME).
  • Page 204 µPD750008 USER'S MANUAL...

  • Page 205: Types Of Interrupt Sources And Vector Tables

    TYPES OF INTERRUPT SOURCES AND VECTOR TABLES Table 6-1 lists the types of interrupt sources, and Figure 6-2 shows vector tables. Interrupt source signal INTBT Reference time interval signal from basic interval timer/wactchdog timer INT4 Detection of both rising and falling edges INT0 Rising/falling edge...
  • Page 206 µPD750008 USER'S MANUAL The column of interrupt priority in Table 6-1 indicates a priority assigned when multiple interrupt requests occur concurrently or are held. A vector table contains interrupt processing start addresses and MBE and RBE setting values during interrupt processing. An assembler pseudo instruction (VENTn) is used to set a vector table. Example A vector table is set for INTBT/INT4.

  • Page 207: Various Devices To Control Interrupt Functions

    6.3 VARIOUS DEVICES TO CONTROL INTERRUPT FUNCTIONS (1) Interrupt request flags and interrupt enable flags The following seven interrupt request flags (IRQxxx) corresponding to the interrupt sources are provided. INT0 interrupt request flag (IRQ0) INT1 interrupt request flag (IRQ1) INT4 interrupt request flag (IRQ4) BT interrupt request flag (IRQBT) An interrupt request flag is set to 1 by an interrupt request, and is automatically cleared to 0 when interrupt processing is performed.

  • Page 208: Set Signals For Interrupt Request Flags

    µPD750008 USER'S MANUAL Table 6-2. Set Signals for Interrupt Request Flags Interrupt request flag IRQBT Set by a reference time interval signal from the basic interval timer/watchdog timer. IRQ4 Set by a detected rising or falling edge of an INT4/P00 pin input signal. IRQ0 Set by a detected edge of an INT0/P10 pin input signal.

  • Page 209: Interrupt Priority Specification Register

    Figure 6-3. Interrupt Priority Specification Register Address FB2H IPS3 IPS2 IPS1 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Symbol IPS0 High-order interrupt selection All low-order interrupt VRQ1 (INTBT/INT4) VRQ2 (INT0) VRQ3 (INT1) VRQ4 (INTCSI) VRQ5 (INTT0) VRQ6 (INTT1) Not to be set Interrupt master enable flag (IME) All interrupts are disabled and no vectored interrupt is activated.
  • Page 210 µPD750008 USER'S MANUAL (3) Configurations of the INT0, INT1, and INT4 circuits (a) As shown in Figure 6-4 (a), the INT0 circuit accepts an external interrupt at its rising or falling edge. The edge to be detected can be selected. The INT0 circuit has a noise elimination function (see Figure 6-5), called a noise eliminator, using a sampling clock, which removes pulses shorter than two sampling clock cycles INT0 circuit may accept pulses which are longer than one sampling clock cycle and shorter than two...

  • Page 211: Configurations Of The Int0, Int1, And Int4 Circuits

    Figure 6-4. Configurations of the INT0, INT1, and INT4 Circuits (a) Configuration of the INT0 circuit INT0/P10 Noise eliminator Selector (b) Configuration of the INT1 circuit INT1/P11 Input buffer (c) Configuration of the INT4 circuit INT4/P00 Input buffer CHAPTER 6 INTERRUPT AND TEST FUNCTIONS IM02 IM03 Input buffer...

  • Page 212: I/O Timing Of A Noise Eliminator

    µPD750008 USER'S MANUAL <1> Shorter than sampling cycle (t INT0 Shaped output <2> 1 to 2 times INT0 Shaped output INT0 Shaped output <3> Longer than 2 times INT0 Shaped output Remark t or 64/f Figure 6-5. I/O Timing of a Noise Eliminator "L"...

  • Page 213: Format Of Edge Detection Mode Registers

    Figure 6-6. Format of Edge Detection Mode Registers (a) INT0 edge detection mode register (IM0) Address FB4H IM03 IM02 IM01 (b) INT1 edge detection mode register (IM1) Address FB5H Caution Changing the edge detection mode register may set an interrupt request flag. So, disable the interrupts before changing the edge detection mode register.

  • Page 214: Interrupt Processing Statuses Of Ist0 And Ist1

    µPD750008 USER'S MANUAL (4) Interrupt status flags The interrupt status flags (IST0 and IST1), which are contained in the PSW, indicate the status of processing currently executed by the CPU. By using the content of these flags, the interrupt priority control circuit controls multiple interrupts as indicated in Table 6-3.

  • Page 215: Interrupt Sequence

    6.4 INTERRUPT SEQUENCE When an interrupt occurs, it is processed using the procedure shown in Figure 6-7. Interrupt (INTxxx) occurrence Corresponding VRQn occurrence Save contents of PC and PSW in stack memory and set data corresponding to activated VRQn to PC, RBE, and MBE. Change contents of IST0 and IST1 from 00 to 01 or from 01 to 10.

  • Page 216: Multiple Interrupt Processing Control

    µPD750008 USER'S MANUAL 6.5 MULTIPLE INTERRUPT PROCESSING CONTROL The µPD750008 can handle multiple interrupts by either of the following methods. (1) Multiple interrupt processing by a high-order interrupt In this method, the µPD750008 selects an interrupt source among multiple interrupt sources, enabling double interrupt processing.

  • Page 217: Multiple Interrupt Processing By Changing The Interrupt Status Flags

    (2) Multiple interrupt processing by changing the interrupt status flags Changing the interrupt status flags with the program causes multiple interrupts to be enabled. That is, when the interrupt processing program changes both IST1 and IST0 to 0 (status 0), multiple interrupt processing is enabled.

  • Page 218: Processing Of Interrupts Sharing A Vector Address

    µPD750008 USER'S MANUAL 6.6 PROCESSING OF INTERRUPTS SHARING A VECTOR ADDRESS Interrupt sources INTBT and INT4 share a vector table, so an interrupt source is selected as described below. (1) Using only one interrupt The interrupt enable flag for desired one of the two interrupt sources sharing a vector table is set to 1, and the interrupt enable flag for the other is cleared to 0.
  • Page 219 Examples 1. To use both INTBT and INT4 as having the higher priority and give priority to INT4 SKTCLR RETI VSUBBT: CLR1 RETI 2. To use both INTBT and INT4 as having the lower priority and give priority to INT4 SKTCLR RETI VSUBBT:...

  • Page 220: Machine Cycles For Starting Interrupt Processing

    µPD750008 USER'S MANUAL 6.7 MACHINE CYCLES FOR STARTING INTERRUPT PROCESSING With the µPD750008 series, the following machine cycles are used to start the execution of the interrupt service routine after an interrupt request flag (IRQn) is set. (1) When IRQn is set during execution of an interrupt control instruction When IRQn is set during execution of an interrupt control instruction, an instruction preceded by that instruction is executed, and an interrupt processing of three machine cycles is executed, then the interrupt service routine is started.
  • Page 221 (2) When IRQn is set during an instruction other than that described in (1) (a) When IRQn is set at the last machine cycle of the instruction being executed In this case, an instruction preceded by the instruction being executed is executed, and an interrupt processing of three machine cycles is executed, then the interrupt service routine is started.

  • Page 222: Effective Use Of Interrupts

    µPD750008 USER'S MANUAL 6.8 EFFECTIVE USE OF INTERRUPTS The interrupt function can be used more effectively in the ways described below. (1) MBE = 0 is set for the interrupt service routine By allocating addresses 00H to 7FH as data memory used by the interrupt service routine and specifying MBE = 0 in an interrupt vector table, the user can code a program without being concerned with a memory bank.
  • Page 223 (1) Interrupt enable/disable <1> Reset <2> EI IE0 <3> EI <4> DI IE0 <5> DI <1> A RESET signal disables all interrupts. <2> Interrupt enable flags are set by the EI IExxx instruction. At this stage, all interrupts are disabled. <3>...
  • Page 224 µPD750008 USER'S MANUAL (2) Example of using INTBT, INT0 (falling edge active), and INTT0 without multiple interrupt processing <2> MOV <3> EI <1> A RESET signal disables all interrupts, setting status 0. <2> INT0 is set to be falling edge active. <3>...
  • Page 225 (3) Nesting of interrupts with higher priority (INTBT has higher priority and INTT0 and INTCSI have lower priority) Reset IEBT IET0 IECSI <1> A, #9 IPS, A <2> INTT0 <1> INTBT is specified as having the higher priority by setting of IPS, and the interrupt is enabled at the same time.
  • Page 226 µPD750008 USER'S MANUAL (4) Execution of held interrupts (interrupt requests when interrupts are disabled) <2> EI <4> <1> If INT0 is set when interrupts are disabled, the interrupt request flag is held. <2> When the interrupt is enabled by the EI instruction, the INT0 interrupt service program starts. <3>...
  • Page 227 (5) Execution of held interrupts – two interrupts with lower priority occur concurrently – <1> When INT0 and INTT0 with the lower priority occur concurrently (during execution of the same instruction), INT0, with a higher priority, is executed first. (INTT0 is held.) <2>...
  • Page 228 µPD750008 USER'S MANUAL (6) Executing pending interrupt – interrupt occurs during interrupt processing (INTBT has higher priority and INTT0 and INTCSI have lower priority) – <1> When INTBT with the higher priority and INTT0 with the lower priority occur at the same time, the processing of the interrupt with the higher priority is started (if there is no possibility that an interrupt with the higher priority occurs while another interrupt with the higher priority is processed, DI IExx is not necessary).
  • Page 229 (7) Enabling of level-two interrupts (enabling level-two INTT0 and INT0 interrupts with INTCSI and INT4 handled as level-one interrupts) <Main program> Reset IET0 IECSI • • • • • • • • • • <1> INTCSI • • • • •...

  • Page 230: Test Function

    µPD750008 USER'S MANUAL 6.10 TEST FUNCTION 6.10.1 Test Sources The µPD750008 has two test sources. INT2 provides two types of edge-detection-test inputs. INT2 (detection of the rising edge of the signal input to the INT2 pin or that of the first falling edge of the signals input to KR0 to KR7) INTW (signal from clock timer) 6.10.2 Hardware to Control Test Functions...
  • Page 231 (2) INT2 and key interrupt (KR0 to KR7) hardware Figure 6-10 shows the configuration of INT2 and KR0 to KR7. The IRQ2 set signal is output in either of the following edge detection modes, which is selected with the INT2 edge detection mode register (IM2). (a) Detection of a rising edge on the INT2 input pin IRQ2 is set when a rising edge is detected on the INT2 input pin.
  • Page 232 µPD750008 USER'S MANUAL...

  • Page 233: Format Of Int2 Edge Detection Mode Register (Im2)

    Figure 6-11. Format of INT2 Edge Detection Mode Register (IM2) Address FB6H IM21 Cautions 1. When the edge detection mode register is modified, test request flags may be set in some cases. So, disable test inputs before modifying the edge detection mode register.
  • Page 234 µPD750008 USER'S MANUAL [MEMO]...

  • Page 235: Chapter 7 Standby Function

    CHAPTER 7 STANDBY FUNCTION The µPD750008 provides a standby function to reduce the power consumption by the system. The standby function is available in the two modes: the STOP mode and HALT mode. Differences between these two modes are as follows: (1) STOP mode In the STOP mode, the main system clock oscillator is stopped, and the entire system stops.

  • Page 236: Setting Of Standby Modes And Operation Status

    µPD750008 USER'S MANUAL 7.1 SETTING OF STANDBY MODES AND OPERATION STATUS Table 7-1. Operation Statuses in the Standby Mode Mode Item Instruction for setting System clock for setting Operation Clock oscillator status Basic interval timer/watchdog timer Serial interface Timer/event counter Timer counter Clock timer External interrupt...

  • Page 237: Release Of The Standby Modes

    Caution 2. Reset all the interrupt request flags before setting the standby mode. If an interrupt source whose interrupt request flag and interrupt enable flag are both set exists, the initiated standby mode is released immediately after it is set (see Figure 6-1). When the STOP mode is set, however, the µPD750008 enters the HALT mode immediately after the STOP instruction is executed, then returns to the operation mode after the wait time specified by the BTM register has elapsed.

  • Page 238: Standby Mode Release Operation

    µPD750008 USER'S MANUAL Figure 7-1. Standby Mode Release Operation (2/2) (c) Release of the HALT mode by RESET signal HALT instruction RESET signal Operating mode Clock (d) Release of the HALT mode by the occurrence of an interrupt HALT instruction Standby release signal...

  • Page 239: Operation After A Standby Mode Is Released

    Table 7-2. Selection of a Wait Time with BTM BTM3 BTM2 BTM1 BTM0 – – – – Other than above Note This time does not include the time from the release of the STOP mode to the start of oscillation. Caution The wait times used when the STOP mode is released do not include the time (a in Figure7- 2) required before clock oscillation is started following the release of the STOP mode, regardless of whether the STOP mode is released by a RESET signal or the generation of...

  • Page 240: Selection Of A Mask Option

    µPD750008 USER'S MANUAL 7.4 SELECTION OF A MASK OPTION For the standby function of the µPD750008, either of the following two values can be selected by a mask option as the wait time during which the start of oscillation deferred from the generation of a RESET signal: <1>...
  • Page 241 <Timing chart> Voltage on V P00/INT4 Operating mode CPU operation <Sample program> (INT4 service program, MBE = 0) VSUB4: PORT0.0 PDOWN SET1 BTM.3 WAIT: IRQBT WAIT PORT0.0 PDOWN A,#0011B PCC,A XA.#xxH PMGm,XA IET0 RETI PDOWN: A,#0 PCC,A XA,#00H PMGA,XA PMGB,XA IET0 A,#1011B BTM,A...
  • Page 242 µPD750008 USER'S MANUAL (2) Application of the HALT mode (at f <Intermittent operation under the following conditions> • The main system clock is switched to the subsystem clock on the falling edge of INT4. • The oscillation of the main system clock is stopped, and HALT mode is set. •...
  • Page 243 <Sample program> (Initialization) A,#0011B PCC,A XA,#05 WM,XA (Main routine) PORT0.0 HALT SKTCLR IRQW MAIN CALL WATCH MAIN: (INT4 service routine) VINT4: PORT0.0 PDOWN CLR1 SCC.3 A,#8 BTM,A WAIT1: IRQBT WAIT1 PORT0.0 PDOWN CLR1 SCC.0 RETI PDOWN: SET1 SCC.0 A,#6 WAIT2: INCS WAIT2 SET1...
  • Page 244 µPD750008 USER'S MANUAL [MEMO]...

  • Page 245: Chapter 8 Reset Function

    CHAPTER 8 RESET FUNCTION The µPD750008 is reset with the external reset signal (RESET) or the reset signal received from the basic interval timer/watchdog timer. When either reset signal is input, the internal reset signal is generated. Figure 8-1 shows the configuration of the reset circuit. Figure 8-1.

  • Page 246: Status Of The Hardware After A Reset

    µPD750008 USER'S MANUAL Table 8-1. Status of the Hardware after a Reset (1/2) Hardware µPD750004 Program counter (PC) µPD750006, µPD750008 µPD75P0016 Carry flag (CY) Skip flags (SK0 to SK2) Interrupt status flags (IST0, IST1) Bank enable flags (MBE, RBE) Stack pointer (SP)
  • Page 247 Table 8-1. Statuses of the Hardware after a Reset (2/2) Hardware Processor clock control register Clock generator, (PCC) clock System clock control register output (SCC) circuit Clock output mode register (CLOM) Sub-oscillator control register (SOS) Interrupt request flag (IRQxxx) Interrupt Interrupt enable flag (IExxx) Priority selection register (IPS) INT0, INT1 and INT2 mode...
  • Page 248 µPD750008 USER'S MANUAL [MEMO]...

  • Page 249: Chapter 9 Writing To And Verifying Program Memory (Prom)

    CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) The program memory in the µPD75P0016 consists of a one-time PROM (16384 x 8 bits). Writing to and verifying the contents of the one-time PROM is accomplished by using the pins shown in the table below.

  • Page 250: Operating Modes When Writing To And Verifying The Program Memory

    µPD75008 USER'S MANUAL OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY If +6 V is applied to the V memory write/verify mode. The specific operating mode is then selected by the setting of the MD0 through MD3 pins as listed in the table below. Operating mode specification +12.5 V +6 V...
  • Page 251 CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) The timing for steps (2) to (12) is shown below. Write DD +1 P40-P43 Data input P50-P53 (P30) (P31) (P32) (P33) Repeat x times Verify Data output Address Additional write increment Data input...

  • Page 252: Reading The Program Memory

    µPD75008 USER'S MANUAL 9.3 READING THE PROGRAM MEMORY The procedure for reading the contents of program memory is described below. The read is performed in the verify mode. (1) Pull low all unused pins to V (2) Apply 5 V to V and V (3) Wait 10 µs.

  • Page 253: Screening Of One-Time Prom

    CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY (PROM) 9.4 SCREENING OF ONE-TIME PROM Because of its structure, it is difficult for NEC to completely test the one-time PROM product before shipment. It is therefore recommended that screening be performed to verify the PROM contents after the necessary data has been written to the PROM and the product has been stored under the following conditions.
  • Page 254 µPD75008 USER'S MANUAL [MEMO]...

  • Page 255: Chapter 10 Mask Option

    10.1 PIN The pins of the µPD750008 have the following mask options: Table 10-1. Selecting Mask Option of Pin P40-P43 Pull-up resistor can be connected in 1-bit units. P50-P53 P40 through P43 (port 4) or P50 through P53 (port 5) can be connected with pull-up resistors by mask option. The mask option can be specified in 1-bit units.

  • Page 256: Mask Option For Feedback Resistor Of Subsystem Clock

    µPD750008 USER'S MANUAL 10.3 MASK OPTION FOR FEEDBACK RESISTOR OF SUBSYSTEM CLOCK For the subsystem clock of the µPD750008, whether to enable the feedback resistor is selected by the mask option. <1> Enable the feedback resistor (switches on or off by software). <2>...

  • Page 257: Chapter 11 Instruction Set

    (6) Table reference instructions suitable for successive references (7) 1-byte relative branch instructions (8) NEC standard mnemonics designed for clarity and readability See Section 3.2 for the addressing modes applicable to data memory manipulation and register banks used for instruction execution.

  • Page 258: Bit Manipulation Instructions

    µPD750008 USER'S MANUAL 11.1.2 Bit Manipulation Instructions With the µPD750008, a variety of instructions are available for bit manipulation. (a) Bit setting: (b) Bit clearing: (c) Bit testing: (d) Bit testing: (e) Bit testing and clearing: SKTCLR mem.bit* (f) Boolean operation: mem.bit* represents a bit address addressed by using a bit manipulation addressing mode (fmem.bit, pmem.@L, or @H+mem.bit).

  • Page 259: Number System Conversion Instructions

    11.1.4 Number System Conversion Instructions An application may need to convert the result of a 4-bit data addition or subtraction (performed in binary) to a decimal number. A time-related application may require sexagesimal conversion. For this reason, the instruction set of the µPD750008 contains number system conversion instructions for converting the result of a 4-bit data addition or subtraction to a number in an arbitrary number system.

  • Page 260: Skip Instructions And The Number Of Machine Cycles Required For A Skip

    µPD750008 USER'S MANUAL 11.1.5 Skip Instructions and the Number of Machine Cycles Required for a Skip The instruction set of the µPD750008 is designed to organize a program by testing a condition with the skip function. When a skip instruction satisfies the skip condition, the immediately following instruction is skipped to execute the instruction immediately after the skipped instruction.

  • Page 261: Instruction Set And Operation

    2-bit immediate data or label FB0H-FBFH and FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label 0000H-0FFFH immediate data or label (µPD750004) 0000H-17FFH immediate data or label (µPD750006) 0000H-1FFFH immediate data or label (µPD750008) 0000H-3FFFH immediate data or label (µPD75P0016)
  • Page 262 µPD750008 USER'S MANUAL (2) Legend A register; 4-bit accumulator B register C register D register E register H register L register X register Register pair (XA), 8-bit accumulator Register pair (BC) Register pair (DE) Register pair (HL) XA’: Extended register pair (XA’) BC’: Extended register pair (BC’) DE’:...
  • Page 263 = 0000H – 0FFFH (PC faddr = 0000H – 07FFH taddr = 0020H – 007FH For MkII mode only addr1 = 0000H – 0FFFH (µPD750004) 0000H – 17FFH (µPD750006) 0000H – 1FFFH (µPD750008) 0000H – 3FFFH (µPD75P0016) Remarks 1. MB represents an accessible memory bank.
  • Page 264 µPD750008 USER'S MANUAL (4) Explanation of the machine cycle column S represents the number of machine cycles required when a skip instruction with the skip function performs a skip operation. S assumes one of the following values: • When no skip operation is performed: S = 0 •...
  • Page 265 Mne- struc- Operation monic tion A,#n4 reg1,#n4 XA,#n8 HL,#n8 rp2,#n8 A,@HL A,@HL+ A,@HL– A,@rpa1 XA,@HL @HL,A @HL,XA A,mem XA,mem mem,A mem,XA A,reg XA,rp’ reg1,A rp’1,XA A,@HL A,@HL+ A,@HL– A,@rpa1 XA,@HL A,mem XA,mem A,reg1 XA,rp’ Number Machine Operation cycle bytes A <– n4 reg1 <–...
  • Page 266 SUBC A,@HL XA,rp’ rp’1,XA Note Set register B to 0 in the µPD750004. Only the LSB is valid in register B in the µPD750006 and µPD750008. Only the low-order two bits are valid in the µPD75P0016. Number Machine Operation...
  • Page 267 Mne- struc- Operand monic tion A,#n4 A,@HL XA,rp’ rp’1,XA A,#n4 A,@HL XA,rp’ rp’1,XA A,#n4 A,@HL XA,rp’ rp’1,XA RORC INCS DECS rp’ reg,#n4 @HL,#n4 A,@HL XA,@HL A,reg XA,rp’ SET1 CLR1 NOT1 Number Machine Operation cycle bytes A <– A n4 A <– A (HL) XA <–...
  • Page 268 µPD750008 USER'S MANUAL Mne- struc- Operand monic tion SET1 mem.bit fmem.bit pmem.@L @H+mem.bit CLR1 mem.bit fmem.bit pmem.@L @H+mem.bit mem.bit fmem.bit pmem.@L @H+mem.bit mem.bit fmem.bit pmem.@L @H+mem.bit SKTCLR fmem.bit pmem.@L @H+mem.bit AND1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit CY,fmem.bit CY,pmem.@L CY,@H+mem.bit XOR1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit Number Machine...
  • Page 269 Note The shaded portion is supported in Mk II mode only. Number Machine Operation cycle bytes — — • µPD750004 <– addr 11-0 The assembler selects the most adequate instruction from instructions below. • BR !addr • BR $addr • BRCB !caddr •...
  • Page 270 2. Only the LSB is valid in register B. 3. Only the low-order two bits are valid in register B. Number Machine Operation cycle bytes • µPD750004 <– addr 11-0 • µPD750006, µPD750008 <– addr 12-0 • µPD75P0016 <– addr 13-0 •...
  • Page 271 2. The shaded portion is supported in Mk II mode only. The other portions are supported in Mk I mode only. Number Machine Operation cycle bytes • µPD750004 <– BCXA 11-0 • µPD750006, µPD750008 <– BCXA 12-0 • µPD75P0016 <– BCXA 13-0 •...
  • Page 272 Note The shaded portion is supported in Mk II mode only. The other portions are supported in Mk I mode only. Number Machine Operation cycle bytes • µPD750004 (SP–3) <– MBE,RBE, 0, 0 (SP–4)(SP–1)(SP–2) <– PC <– addr, SP <– SP–4 11-0 • µPD750006, µPD750008 (SP–3) <– MBE,RBE, 0, PC (SP–4)(SP–1)(SP–2) <–...
  • Page 273 Note The shaded portion is supported in Mk II mode only. The other portions are supported in Mk I mode only. Number Machine Operation cycle bytes • µPD750004 (SP–2) –> x, x, MBE,RBE (SP–6)(SP–3)(SP–4) <– PC (SP–5) <– 0, 0, 0, 0 <– 0+faddr, SP <– SP–6 11-0 • µPD750006, µPD750008 (SP–2) –>...
  • Page 274 Note The shaded portion is supported in Mk II mode only. The other portions are supported in Mk I mode only. Number Machine Operation cycle bytes • µPD750004 MBE, RBE, 0, 0 <– (SP+1) <– (SP)(SP+3)(SP+2) 11-0 SP <– SP+4 Then skip unconditionally • µPD750006, µPD750008 MBE, 0, 0, PC <–...
  • Page 275 2. MBE = 0, or MBE = 1 and MBS = 15 must be set when an IN/OUT instruction is executed. Number Machine Operation cycle bytes • µPD750004 0, 0, 0, 0 <– (SP+1) <– (SP)(SP+3)(SP+2) 11-0 PSW <– (SP+4)(SP+5), SP <– SP+6 • µPD750006, µPD750008 0, 0, 0, PC <–...
  • Page 276 Machine Operation cycle bytes RBS <– n (n=0 - 3) MBS <– n (n=0, 1, 15) • µPD750004 When the TBR instruction is used <– (taddr) 11-0 When the TCALL instruction is used (SP–4)(SP–1)(SP–2) <– PC (SP–3) <– MBE, RBE, 0, 0 <–...
  • Page 277 2. The TBR and TCALL instructions are assembler pseudo instructions to define tables used for GETI instructions. Number Machine Operation cycle bytes • µPD750004 When the TBR instruction is used <– (taddr) 11-0 When the TCALL instruction is used (SP–6)(SP–3)(SP–4) <– PC (SP–5) <– 0, 0, 0, 0 (SP–2) <–...

  • Page 278: Instruction Codes Of Each Instruction

    µPD750008 USER'S MANUAL 11.3 INSTRUCTION CODES OF EACH INSTRUCTION (1) Explanations of the symbols for the instruction codes : Immediate data for n4 or n8 : Immediate data for mem : Immediate data for bit : Immediate data for n or IExxx : Immediate data for taddr x 1/2 : Immediate data for the address (2 to 16) relative to branch destination address minus one : Immediate data for the one’s complement of the address (15 to 1) relative to the branch destination...
  • Page 279 (2) Bit manipulation addressing instruction codes 1 in the operand field indicates that there are three types of bit manipulation addressing, fmem.bit, pmem.@L, and @H+mem.bit. The table below lists the second byte Second byte of instruction code fmem.bit pmem.@L @H+mem.bit : Immediate data for bit : Immediate data for fmem (Low-order four bits of address) : Immediate data for pmem (Bits 2 to 5 of address)
  • Page 280 µPD750008 USER'S MANUAL Mne- Instruction Operand monic Transfer A,#n4 reg1,#n4 rp,#n8 A,@rpa1 XA,@HL @HL,A @HL,XA A,mem XA,mem mem,A mem,XA A,reg XA,rp’ reg1,A rp’1,XA A,@rpa1 XA,@HL A,mem XA,mem A,reg1 XA,rp’ MOVT XA,@PCDE Table reference XA,@PCXA XA,@BCXA XA,@BCDE MOV1 transfer 1 ,CY 0 1 1 1 I 1 0 0 1 1 0 1 0 1 0 0 0 1 P...
  • Page 281 Mne- Instruction Operand monic Arithmetic/ ADDS A,#n4 logical XA,#n8 A,@HL XA,rp’ rp’1,XA ADDC A,@HL XA,rp’ rp’1,XA SUBS A,@HL XA,rp’ rp’1,XA SUBC A,@HL XA,rp’ rp’1,XA A,#n4 A,@HL XA,rp’ rp’1,XA A,#n4 A,@HL XA,rp’ rp’1,XA A,#n4 A,@HL XA,rp’ rp’1,XA Accumulator RORC manipulation 0 1 1 0 I 1 0 1 1 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0...
  • Page 282 µPD750008 USER'S MANUAL Mne- Instruction Operand monic Increment/ INCS decrement DECS rp’ reg,#n4 Comparison @HL,#n4 A,@HL XA,@HL A,reg XA,rp’ Carry flag SET1 manipu- CLR1 lation NOT1 Memory SET1 mem.bit manipu- CLR1 mem.bit lation mem.bit mem.bit SKTCLR AND1 XOR1 1 1 0 0 0 R 1 0 0 0 1 P 1 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0...
  • Page 283 Mne- Instruction Operand monic Branch !addr $addr1 (+16) to (+2) (–1) to (–15) 1 1 1 1 S PCDE PCXA BCDE BCXA !addr1 BRCB !caddr Sub- CALL !addr routine CALLA !addr1 stack CALLF !faddr control RETS RETI PUSH A,PORTn XA,PORTn PORTn,A PORTn,XA Interrupt...

  • Page 284: Functions And Applications Of The Instructions

    Mk II mode. Read the following explanation. How to read Can be used in both Mk I mode and Mk II mode for the µPD750004, µPD750006, µPD750008, and µPD75P0016 Can be used in only Mk I mode for the µPD750004, µPD750006, µPD750008, and µPD75P0016 Can be used in only Mk II mode for the µPD750004, µPD750006, µPD750008, and µPD75P0016...
  • Page 285 MOV reg1,#n4 Function: reg1 <– n4 n4 = I Transfers the 4-bit immediate data n4 to A register reg1 (X, H, L, D, E, B, C). MOV XA,#n8 Function: XA <– n8 n8 = I Transfers the 8-bit immediate data n8 to register pair XA. The string effect can be utilized. When two or more of this instruction are executed in succession or when MOV A,#n4 instruction is located continguously, the string instructions following an executed instruction are processed as NOP instructions.
  • Page 286 µPD750008 USER'S MANUAL Then skips the immediately following instruction. When HL– (automatic decrement) is specified for the register pair, automatically decrements the contents of the L register by one after the data transfer, and continues the operation until the contents are set to FH. Then skips the immediately following instruction.
  • Page 287 MOV XA,mem Function: A <– (mem), X <– (mem+1) Transfers the data at the data memory location addressed by the 8-bit immediate data mem to the A register, and transfers the data at the next address to the X register. An even address can be specified with mem.
  • Page 288 µPD750008 USER'S MANUAL MOV reg1,A Function: reg1 <– A Transfers the contents of the A register to register reg1 (X, H, L, D, E, B, C). MOV rp’1,XA Function: rp’1 <– XA Transfers the contents of the XA register pair to register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, BC’). XCH A,@HL XCH A,@HL+ XCH A,@HL–...
  • Page 289 XCH XA,@HL Function: A <–> (HL), X <–> (HL+1) Exchanges the contents of the A register with the data at the data memory location addressed by the HL register pair, and exchanges the contents of the X register with the data at the next memory address. However, if the contents of the L register are odd- numbered, an address with the low-order bit ignored is specified.

  • Page 290: Table Reference Instructions

    Remark "Function" in this section is applicable to the µPD750006 and µPD750008 whose program counters consist of 13 bits each. This is also applicable to the µPD750004 whose program counter consists of 12 bits and the µPD75P0016 whose program counter consists of 14 bits, however.
  • Page 291 Remark "Function" in this section is applicable to the µPD750006 and µPD750008 whose program counters consist of 13 bits each. This is also applicable to the µPD750004 whose program counter consists of 12 bits and the µPD75P0016 whose program counter consists of 14 bits, however.
  • Page 292 Remark "Function" in this section is applicable to the µPD750006 and µPD750008 whose program counters consist of 13 bits each. This is also applicable to the µPD750004 whose program counter consists of 12 bits and the µPD75P0016 whose program counter consists of 14 bits, however.

  • Page 293: Bit Transfer Instructions

    11.4.3 Bit Transfer Instructions MOV1 CY,fmem.bit MOV1 CY,pmem.@l MOV1 CY,@H+mem.bit Function: CY <– (bit specified in operand) Transfers the data memory bit specified by bit manipulation addressing (fmem.bit, pmem.@L, @H+mem.bit) to the carry flag (CY). MOV1 fmem.bit,CY MOV1 pmem.@L,CY MOV1 @H+mem.bit,CY Function: (bit specified in operand) <–...
  • Page 294 µPD750008 USER'S MANUAL ADDS XA,#n8 Function: XA <– XA+n8 ; Skip if carry. Adds the 8-bit immediate data n8 to the contents of the XA register pair in binary, then skips the next instruction if the addition generates a carry. The carry flag is not affected. ADDS A,@HL Function: A <–...
  • Page 295 ADDC XA,rp’ Function: XA, CY <– XA+rp’+CY Adds the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, BC’) together with the carry flag to the contents of the XA register pair in binary. If the addition generates a carry, the carry flag is set. If no carry is generated, the carry flag is reset.
  • Page 296 µPD750008 USER'S MANUAL SUBS rp’1,XA Function: rp’1 <– rp’1+XA ; Skip if borrow Subtracts the contents of the XA register pair from the contents of register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, BC’), then sets the result in register pair rp’1. If the subtraction generates a borrow, the immediately following instruction is skipped.
  • Page 297 AND A,@HL Function: A <– A (HL) ANDs the contents of the A register with the data at the data memory location addressed by the HL register pair, then sets the result in the A register. AND XA,rp’ Function: XA <– XA rp’ ANDs the contents of the XA register pair with the contents of register pair rp’...
  • Page 298 µPD750008 USER'S MANUAL OR rp’1,XA Function: rp’1 <– rp’ XA ORs the contents of register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, BC’) with the contents of the XA register pair, then sets the result in register pair rp’1. XOR A,#n4 Function: A <–...

  • Page 299: Accumulator Manipulation Instructions

    11.4.5 Accumulator Manipulation Instructions RORC A Function: CY <- A Rotates the contents of the A register (4-bit accumulator) through the carry flag one bit position to the right. NOT A Function: A <– A Obtains the one’s complement of the A register (4-bit accumulator), that is, inverts each bit of the A register. 11.4.6 Increment/Decrement Instructions INCS reg Function: reg <–...

  • Page 300: Compare Instructions

    µPD750008 USER'S MANUAL INCS mem Function: (mem) <– (mem)+1 ; Skip if (mem) = 0, mem = D Increments the data at the data memory location addressed by the 8-bit immediate data mem. If the result of increment produces data that is 0, the immediately following instruction is skipped. DECS reg Function: reg <–...

  • Page 301: Carry Flag Manipulation Instructions

    SKE XA,@HL Function: Skip if A = (HL) and X = (HL+1) Skips the immediately following instruction if the contents of the A register match the data at the data memory location addressed by the HL register pair, and the contents of the X register match the data at the next address in data memory.

  • Page 302: Memory Bit Manipulation Instructions

    µPD750008 USER'S MANUAL NOT1 CY Function: CY <– CY Inverts the carry flag. If it is 0, it is set to 1, or vice versa. 11.4.9 Memory Bit Manipulation Instructions SET1 mem.bit Function: (mem.bit) <– 1 Sets the bit specified by the 2-bit immediate data bit at the address specified by the 8-bit immediate data mem.
  • Page 303 Skips the immediately following instruction if the bit specified by the 2-bit immediate data bit at the address specified by the 8-bit immediate data mem is 1. SKT fmem.bit SKT pmem.@L SKT @H+mem.bit Function: Skip if (bit specified in operand) = 1 Skips the immediately following instruction if the bit in data memory specified by bit manipulation addressing (fmem.bit, pmem.@L, @H+mem.bit) is set to 1.

  • Page 304: Branch Instructions

    µPD750008 USER'S MANUAL AND1 CY, fmem.bit AND1 CY, pmem.@L AND1 CY, @H+mem.bit Function: CY <– CY (bit specified in operand) ANDs the content of the carry flag with the bit in data memory specified by bit manipulation addressing (fmem.bit, pmem.@L, @H+mem.bit), then sets the result in the carry flag. OR1 CY, fmem.bit OR1 CY, pmem.@L OR1 CY, @H+mem.bit...
  • Page 305 Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of 13 bits (addr = 0000H to 1FFFH). However, this is also applicable to the µPD750004 whose program counter consists of 12 bits (addr = 0000H to 0FFFH), the µPD750006 whose program counter consists of 13 bits (addr = 0000H to 17FFH), and the µPD75P0016 whose program counter consists of...
  • Page 306 ) have been replaced with the 12-bit immediate data caddr (A 11-0 Since the program counter of the µPD750004 consists of 11 bits, this instruction enables a branch to any location in the program memory space. In the µPD750006 and µPD750008, PC Similarly, in the µPD75P0016, PC...
  • Page 307 Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of 13 bits (addr = 0000H to 1FFFH). However, this is also applicable to the µPD750004 whose program counter consists of 12 bits (addr = 0000H to 0FFFH), the µPD750006 whose program counter consists of 13 bits (addr = 0000H to 17FFH), and the µPD75P0016 whose program counter consists of 14 bits...
  • Page 308 Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of 13 bits (addr = 0000H to 1FFFH). However, this is also applicable to the µPD750004 whose program counter consists of 12 bits (addr = 0000H to 0FFFH), the µPD750006 whose program counter consists of 13 bits (addr = 0000H to 17FFH), and the µPD75P0016 whose program counter consists of 14 bits...

  • Page 309: Subroutine Stack Control Instructions

    Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of 13 bits (addr = 0000H to 1FFFH). However, this is also applicable to the µPD750004 whose program counter consists of 12 bits (addr = 0000H to 0FFFH), the µPD750006 whose program counter consists of 13 bits (addr = 0000H to 17FFH), and the µPD75P0016 whose program counter consists of 14 bits...
  • Page 310 Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of 13 bits (addr = 0000H to 1FFFH). However, this is also applicable to the µPD750004 whose program counter consists of 12 bits (addr = 0000H to 0FFFH), the µPD750006 whose program counter consists of 13 bits (addr = 0000H to 17FFH), and the µPD75P0016 whose program counter consists of 14 bits...
  • Page 311 Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of 13 bits (addr = 0000H to 1FFFH). However, this is also applicable to the µPD750004 whose program counter consists of 12 bits (addr = 0000H to 0FFFH), the µPD750006 whose program counter consists of 13 bits (addr = 0000H to 17FFH), and the µPD75P0016 whose program counter consists of 14 bits...
  • Page 312 Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of 13 bits (addr = 0000H to 1FFFH). However, this is also applicable to the µPD750004 whose program counter consists of 12 bits (addr = 0000H to 0FFFH),the µPD750006 whose program counter consists of 13 bits (addr = 0000H to 17FFH),and the µPD75P0016 whose program counter consists of 14 bits...

  • Page 313: Interrupt Control Instructions

    PUSH BS Function: (SP–1) <– MBS, (SP–2) <– RBS, SP <– SP–2 Saves the contents of the memory bank select register (MBS) and the register bank select register (RBS) to the data memory location (stack) addressed by the stack pointer (SP), then decrements SP. POP rp Function: rp <–...

  • Page 314: I/O Instructions

    µPD750008 USER'S MANUAL DI IExxx Function: IExxx <– 0 xxx = N Resets an interrupt enable flag (IExxx) to 0 to disable an interrupt. (xxx = BT, CSI, T0, T1, W, 0, 1, 2, 4) 11.4.13 I/O Instructions IN A,PORTn Function: A <–...

  • Page 315: Cpu Control Instructions

    Caution Before this instruction can be executed, MBE = 0 or (MBE = 1, MBS = 15) must be set. Only 4 or 6 can be specified as n. 11.4.14 CPU Control Instructions HALT Function: PCC.2 <– 1 Sets the HALT mode. (This instruction is used to set bit 2 of the processor clock control register.) Caution The instruction immediately following a HALT instruction must be a NOP instruction.
  • Page 316 Remark "Function" in this section is applicable to the µPD750008 whose program counter consists of 13 bits (addr = 0000H to 1FFFH). However, this is also applicable to the µPD750004 whose program counter consists of 12 bits (addr = 0000H to 0FFFH), the µPD750006 whose program counter consists of 13 bits (addr = 0000H to 17FFH), and the µPD75P0016 whose program counter consists of 14 bits...
  • Page 317 Caution All 2-byte instructions (except the BRCB instruction and CALLF instruction) set in the reference table must be 2-machine-cycle instructions. Pairs of 1-byte instructions can be set as indicated in the table below. MOV A,@HL MOV @HL,A XCH A,@HL MOV A,@DE XCH A,@DE MOV A,@DL XCH A,@DL...
  • Page 318 µPD750008 USER'S MANUAL Example MOV HL, #00H MOV XA, #FFH are replaced with GETI instructions. CALL SUB1 SUB2 HL00: XAFF: CSUB1: TCALL BSUB2: · · · · · · · · · · GET HL00 · · · · · ·...

  • Page 319: Appendix Afunctions Of The Μpd75008, Μpd750008, And Μpd75P0016

    APPENDIX A FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016 Item Program memory Data memory Oscillation settling time When selecting the main system clock When selecting the subsys- tem clock 20 (CU) 38 (GB) 24 (CU) 42 (GB) 6 - 9 (CU) 23-26 (GB) SBS register Stack area...
  • Page 320 µPD750008 USER'S MANUAL Item Timer Clock output (PCL) BUZ output (BUZ) Serial interface Feedback resistor cut flag (SOS.0) Sub-oscillator current cut flag (SOS.1) Register bank selection register (RBS) Standby release with INT0 Number of vectored interrupts Processor clock control register Power supply voltage Operating ambient temperature Package...

  • Page 321: Appendix Bdevelopment Tools

    APPENDIX B DEVELOPMENT TOOLS The following development tools are provided for the development of a system which employs the µPD750008. In the 75XL series, use the common relocatable assembler together with a device file of each model. RA75X relocatable assembler Device file Note These software products cannot use the task swap function, which is available in MS-DOS Ver.
  • Page 322 µPD750008 USER'S MANUAL PROM programming tools Hardware PG-1500 PA-75P008CU Software PG-1500 controller Note These software products cannot use the task swap function, which is available in MS-DOS Ver. 5.00 or later. Remark Operation of the PG-1500 controller is guaranteed only on the above host machines and OSs. The PG-1500 PROM programmer is used together with an accessory board and optional program adapter.
  • Page 323 Debugging Tools The in-circuit emulators (IE-75000-R and IE-75001-R) are provided to debug programs used for the µPD750008. The following system is shown below. Note 1 IE-75000-R IE-75001-R Note 2 IE-75300-R-EM EP-75008GB-R EV-9200G-44 EP-75008CU-R IE control program Notes 1. Maintenance service only 2.
  • Page 324 µPD750008 USER'S MANUAL OS for IBM PC The following IBM PC OSs are supported. PC DOS MS-DOS IBM DOS Note Only English version is supported. Caution These software products cannot use the task swap function, which is available in MS-DOS Ver.
  • Page 325 APPENDIX B DEVELOPMENT TOOLS...

  • Page 326: B-1 Drawings Of The Ev-9200G-44 (Reference)

    µPD750008 USER'S MANUAL Drawings of the Conversion Socket (EV-9200G-44) and Recommended Pattern on Boards Figure B-1. Drawings of the EV-9200G-44 (Reference) EV-9200G-44-G0...

  • Page 327: B-2 Recommended Pattern On Boards For The Ev-9200G-44 (Reference)

    APPENDIX B DEVELOPMENT TOOLS Figure B-2. Recommended Pattern on Boards for the EV-9200G-44 (Reference) EV-9200G-44-P0 Caution Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"...
  • Page 328 µPD750008 USER'S MANUAL [MEMO]...

  • Page 329: Appendix Cmasked Rom Ordering Procedure

    • Masked ROM order check sheet • Mask option information sheet <4> Ordering Send a set of the media created in <2> and the documents created in <3> to a special agent or NEC’s Sales Department by the date indicated in the advance notice.
  • Page 330 µPD750008 USER'S MANUAL [MEMO]...

  • Page 331: Appendix Dinstruction Index

    APPENDIX D INSTRUCTION INDEX D.1 INSTRUCTION INDEX (BY FUNCTION) [Transfer instructions] A,#n4 ... 245, 264 reg1,#n4 ... 245, 265 XA,#n8 ... 245, 265 HL,#n8 ... 245, 265 rp2,#n8 ... 245, 265 A,@HL ... 245, 265 A,@HL+ ... 245, 265 A,@HL– ... 245, 265 A,@rpa1 ...
  • Page 332 µPD750008 USER'S MANUAL A,@HL ... 247, 277 XA,rp’ ... 247, 277 rp’1,XA ... 247, 278 A,#n4 ... 247, 278 A,@HL ... 247, 278 XA,rp’ ... 247, 278 rp’1,XA ... 247, 278 [Accumulator manipulation instructions] RORC A ... 247, 279 A ... 247, 279 [Increment/decrement instructions] INCS reg ...
  • Page 333 !addr1 ... 251, 285 BRCB !caddr ... 251, 286 addr ... 256, 288 [Subroutine stack control instructions] CALLA !addr1 ... 251, 289 CALL !addr ... 252, 289 CALLF !faddr ... 252, 290 TCALL !addr ... 256, 290 RET ... 253, 291 RETS ...

  • Page 334: Instruction Index (Alphabetical Order)

    µPD750008 USER'S MANUAL D.2 INSTRUCTION INDEX (ALPHABETICAL ORDER) ADDC A,@HL ... 246, 274 ADDC rp’1,XA .. 246, 275 ADDC XA,rp’ ... 246, 275 ADDS A,#n4 ... 246, 273 ADDS A,@HL ... 246, 274 ADDS rp’1,XA ... 246, 274 ADDS XA,rp’ ... 246, 274 ADDS XA,#n8 ...
  • Page 335 A,@rpa1 ... 245, 265 HL,#n8 ... 245, 265 mem,A ... 245, 267 mem,XA ... 245, 267 reg1,A ... 245, 268 reg1,#n4 ... 245, 265 rp’1,XA ... 245, 268 rp2,#n8 ... 245, 265 XA,mem ... 245, 267 XA,rp’ ... 245, 267 XA,#n8 ...
  • Page 336 µPD750008 USER'S MANUAL pmem.@L ... 248, 283 @H+mem.bit ... 248, 283 SKTCLR fmem.bit ... 248, 283 SKTCLR pmem.@L ... 248, 283 SKTCLR @H+mem.bit ... 248, 283 STOP ... 255, 295 SUBC A,@HL ... 246, 276 SUBC rp’1,XA ... 246, 276 SUBC XA,rp’...

  • Page 337: Appendix E Hardware Index

    APPENDIX E HARDWARE INDEX E.1 HARDWARE INDEX (ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE NAME) Acknowledge detection flag ... 132 Acknowledge enable bit ... 132 Acknowledge trigger bit ... 132 Bank select register ... 65 Basic interval timer ... 99 Basic interval timer mode register ...
  • Page 338 µPD750008 USER'S MANUAL Register bank enable flag ... 34, 64 Register bank select register ... 34, 65 Serial bus interface control register ... 131 Serial interface interrupt enable flag ... 187 Serial interface interrupt request flag ... 187 Serial interface operation enable/disable specification bit ...

  • Page 339: Hardware Index

    E.2 HARDWARE INDEX (ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE SYMBOL) ACKD ... 132 ACKE ... 132 ACKT ... 132 BS ... 65 BSB0-BSB3 ... 181 BSYE ... 132 BT ... 99 BTM ... 99 CLOM ... 97 CMDD ... 132 CMDT ...
  • Page 340 µPD750008 USER'S MANUAL SBIC ... 131 SBS ... 46, 58 SCC ... 88 SIO ... 134 SK0, SK1, SK2 ... 63 SOS ... 93 SP ... 58 SVA ... 134 T0 ... 109 T1 ... 110 TOE0 ... 114 TOE1 ... 114 TM0 ...

  • Page 341: Appendix F Revision History

    APPENDIX F REVISION HISTORY Major revisions in this edition are shown below. The revised chapters refer to this edition. Edition Major revisions from previous edition Second The 44-pin plastic QFP package was changed from µPD750008GB-xxx-3B4 to µPD750008GB-xxx-3BS-MTX. The µPD75P0016 under development has been changed to the already-developed µPD75P0016.
  • Page 342 µPD750008 USER'S MANUAL [MEMO]...

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