NEC VR4181 mPD30181 Manuals

Manuals and User Guides for NEC VR4181 mPD30181. We have 1 NEC VR4181 mPD30181 manual available for free PDF download: User Manual

NEC VR4181 mPD30181 User Manual (444 pages)

64-/32-Bit Microprocessor Hardware

Brand: NEC | Category: Computer Hardware | Size: 1.49 MB

- 13
  Table of Contents
29
Chapter 1 Introduction
- 29
  Features
- 30
  Ordering Information
- 30
  R 4181 Key Features
- 30
  Internal Block Diagram
  - 31
    CPU Core
  - 31
    Bus Interface
  - 32
    Memory Interface
  - 32
    DMA Controller (DCU)
  - 32
    Interrupt Controller (ICU)
  - 32
    Real-Time Clock
  - 32
    Audio Output (D/A Converter)
  - 32
    Touch Panel Interface and Audio Input (A/D Converter)
  - 33
    Clocked Serial Interface (CSI)
  - 33
    Keyboard Interface (KIU)
  - 33
    General-Purpose I/O
  - 34
    Programmable Chip Selects
  - 34
    LCD Interface
  - 35
    Wake-Up Events
  - 35
    R 4110 CPU Core
- 35
  R 4110 CPU Core Internal Block Diagram
  - 37
    CPU Registers
  - 38
    CPU Instruction Set Overview
- 38
  CPU Instruction Formats (32-Bit Length Instruction)
- 39
  CPU Instruction Formats (16-Bit Length Instruction)
  - 40
    Data Formats and Addressing
- 41
  Byte Address in Little-Endian Byte Order
- 42
  Unaligned Word Accessing (Little Endian)
  - 43
    CP0 Registers
  - 44
    Floating-Point Unit (FPU)
  - 44
    Memory Management Unit
  - 44
    Cache
  - 44
    Instruction Pipeline
  - 45
    Power Modes
  - 46
    Code Compatibility
  - 47
    Clock Interface
- 48
  External Circuits of Clock Oscillator
- 49
  Incorrect Connection Circuits of Resonator
50
Chapter 2 Pin Functions
- 50
  Pin Configuration
- 52
  Pin Function Description
- 60
  Pin Status in Specific Status
- 63
  Recommended Connection of Unused Pins and I/O Circuit Types
- 66
  Pin I/O Circuits
67
Chapter 3 Cp0 Registers
- 67
  Coprocessor 0 (CP0)
- 69
  Details of CP0 Registers
  - 69
    Index Register
  - 69
    Random Register (1)
- 69
  Random Register
  - 70
    Entrylo0 (2) and Entrylo1 (3) Registers
- 70
  Entrylo0 and Entrylo1 Registers
  - 71
    Context Register (4)
- 71
  Context Register
  - 72
    Pagemask Register (5)
- 72
  Pagemask Register
  - 73
    Wired Register
- 73
  Positions Indicated By the Wired Register
  - 74
    Badvaddr Register (8)
  - 74
    Count Register
- 74
  Badvaddr Register
  - 75
    Entryhi Register (10)
- 75
  Entryhi Register
  - 76
    Compare Register (11)
  - 76
    Status Register (12)
- 76
  Compare Register
- 76
  Status Register
- 77
  Status Register Diagnostic Status Field
  - 79
    Cause Register
  - 81
    Exception Program Counter (EPC) Register (14)
- 81
  EPC Register (When MIPS16 ISA Is Disabled)
  - 82
    Processor Revision Identifier (Prid) Register (15)
- 82
  EPC Register (When MIPS16 ISA Is Enabled)
- 82
  Prid Register
  - 83
    Config Register (16)
- 83
  Config Register
  - 84
    Load Linked Address (Lladdr) Register (17)
- 84
  Lladdr Register
  - 85
    Watchlo (18) and Watchhi (19) Registers
- 85
  Watchlo Register
- 85
  Watchhi Register
  - 86
    Xcontext Register (20)
- 86
  Xcontext Register
  - 87
    Parity Error Register (26)
  - 87
    Cache Error Register (27)
- 87
  Parity Error Register
- 87
  Cache Error Register
  - 88
    Taglo (28) and Taghi (29) Registers
- 88
  Taglo Register
- 88
  Taghi Register
  - 89
    Errorepc Register (30)
- 90
  Errorepc Register (When MIPS16 ISA Is Disabled)
- 90
  Errorepc Register (When MIPS16 ISA Is Enabled)
91
Chapter 4 Memory Management System
- 91
  Overview
- 92
  Physical Address Space
- 92
  R 4181 Physical Address Space
  - 93
    ROM Space
  - 93
    External System Bus Space
  - 94
    Internal I/O Space
  - 95
    DRAM Space
96
Chapter 5 Initialization Interface
- 96
  Reset Function
  - 97
    RTC Reset
  - 98
    RSTSW Reset
  - 99
    Deadman's Switch Reset
  - 100
    Software Shutdown
  - 101
    Haltimer Shutdown
- 102
  Power-On Sequence
- 102
  R 4181 Activation Sequence (When Activation Is OK)
- 103
  R 4181 Activation Sequence (When Activation Is NG)
  - 104
    Reset of CPU Core
    - 104
      Cold Reset
    - 105
      Soft Reset
  - 106
    Notes On Initialization
    - 106
      CPU Core
    - 106
      Internal Peripheral Units
    - 107
      Returning From Power Mode
108
Chapter 6 Bus Control
- 108
  MBA Host Bridge
- 108
  R 4181 Internal Bus Structure
  - 109
    MBA Host Bridge ROM and Register Address Space
  - 109
    MBA Modules Address Space
  - 110
    Bus Control Registers
    - 111
      BCUCNTREG1 (0X0A00 0000)
    - 112
      CMUCLKMSK (0X0A00 0004)
    - 113
      BCUSPEEDREG (0X0A00 000C)
- 114
  ROM Read Cycle and Access Parameters
  - 115
    BCURFCNTREG (0X0A00 0010)
  - 116
    REVIDREG (0X0A00 0014)
  - 117
    CLKSPEEDREG (0X0A00 0018)
  - 118
    ROM Interface
    - 118
      External ROM Devices Memory Mapping
    - 119
      Connection to External ROM (X 16) Devices
    - 120
      Example of ROM Connection
    - 125
      External ROM Cycles
- 125
  Ordinary ROM Read Cycle (WROMA(3:0) = 0101)
- 126
  Pagerom Read Cycle (WROMA(3:0) = 0011, WPROM(2:0) = 001)
- 127
  Flash Memory Read Cycle (Rtype(1:0) = 01, WROMA(3:0) = 0101)
- 127
  Flash Memory Write Cycle (Rtype(1:0) = 01, WROMA(3:0) = 0100)
  - 128
    DRAM Interface
    - 128
      EDO DRAM Configuration
- 128
  External EDO DRAM Configuration
  - 129
    Mixed Memory Mode (EDO DRAM Only)
  - 129
    EDO DRAM Timing Parameters
  - 130
    SDRAM Configuration
  - 131
    Memory Controller Register Set
    - 131
      EDOMCYTREG (0X0A00 0300)
    - 133
      MEMCFG_REG (0X0A00 0304)
    - 135
      MODE_REG (0X0A00 0308)
    - 136
      SDTIMINGREG (0X0A00 030C)
  - 137
    ISA Bridge
  - 137
    ISA Bridge Register Set
    - 138
      ISABRGCTL (0X0B00 02C0)
    - 139
      ISABRGSTS (0X0B00 02C2)
    - 140
      XISACTL (0X0B00 02C4)
142
Chapter 7 Dma Control Unit (Dcu)
- 142
  General
- 144
  DCU Registers
  - 145
    Microphone Destination 1 Address Registers
  - 146
    Microphone Destination 2 Address Registers
  - 147
    Speaker Source 1 Address Registers
  - 148
    Speaker Source 2 Address Registers
  - 149
    DMARSTREG (0X0A00 0040)
  - 149
    AIUDMAMSKREG (0X0A00 0046)
  - 150
    MICRCLENREG (0X0A00 0658)
  - 150
    SPKRCLENREG (0X0A00 065A)
  - 151
    MICDMACFGREG (0X0A00 065E)
  - 152
    SPKDMACFGREG (0X0A00 0660)
  - 153
    DMAITRQREG (0X0A00 0662)
  - 154
    DMACTLREG (0X0A00 0664)
  - 155
    DMAITMKREG (0X0A00 0666)
156
Chapter 8 Clocked Serial Interface Unit (Csi)
- 156
  Overview
- 156
  Operation of CSI
  - 156
    Transmit/Receive Operations
  - 157
    SCK Phase and CSI Transfer Timing
- 157
  SCK and SI/SO Relationship
  - 159
    CSI Transfer Types
  - 160
    Transmit and Receive Fifos
  - 160
    CSI Registers
    - 161
      CSIMODE (0X0B00 0900)
    - 163
      CSIRXDATA (0X0B00 0902)
    - 163
      CSITXDATA (0X0B00 0904)
    - 164
      CSILSTAT (0X0B00 0906)
    - 166
      CSIINTMSK (0X0B00 0908)
    - 167
      CSIINTSTAT (0X0B00 090A)
    - 169
      CSITXBLEN (0X0B00 090C)
    - 170
      CSIRXBLEN (0X0B00 090E)
171
Chapter 9 Interrupt Control Unit (Icu)
- 171
  Overview
- 172
  Outline of Interrupt Control
  - 173
    Register Set
    - 174
      SYSINT1REG (0X0A00 0080)
    - 176
      MSYSINT1REG (0X0A00 008C)
    - 178
      NMIREG (0X0A00 0098)
    - 179
      SOFTINTREG (0X0A00 009A)
    - 180
      SYSINT2REG (0X0A00 0200)
    - 181
      MSYSINT2REG (0X0A00 0206)
    - 182
      PIUINTREG (0X0B00 0082)
    - 183
      AIUINTREG (0X0B00 0084)
    - 184
      KIUINTREG (0X0B00 0086)
    - 185
      MPIUINTREG (0X0B00 008E)
    - 186
      MAIUINTREG (0X0B00 0090)
    - 187
      MKIUINTREG (0X0B00 0092)
188
Chapter 10 Power Management Unit (Pmu)
- 188
  General
- 188
  R 4181 Power Mode
  - 188
    Power Mode and State Transition
  - 189
    R 4181 Power Mode
- 191
  Reset Control
  - 191
    RTC Reset
  - 192
    RSTSW Reset
  - 192
    Deadman's Switch Reset
  - 192
    Preserving DRAM Data On RSTSW Reset
- 192
  EDO DRAM Signals On RSTSW Reset (SDRAM Bit = 0)
  - 193
    Shutdown Control
    - 193
      Haltimer Shutdown
    - 193
      Software Shutdown
    - 193
      BATTINH Shutdown
  - 194
    Power-On Control
    - 195
      Activation Via Power Switch Interrupt Request
- 195
  Activation Via Power Switch Interrupt Request (BATTINH = H)
- 195
  Activation Via Power Switch Interrupt Request (BATTINH = L)
  - 196
    Activation Via Compactflash Interrupt Request
- 196
  Activation Via Compactflash Interrupt Request (BATTINH = H)
- 196
  Activation Via Compactflash Interrupt Request (BATTINH = L)
  - 197
    Activation Via GPIO Activation Interrupt Request
- 197
  Activation Via GPIO Activation Interrupt Request (BATTINH = H)
- 197
  Activation Via GPIO Activation Interrupt Request (BATTINH = L)
  - 198
    Activation Via DCD Interrupt Request
- 199
  Activation Via DCD Interrupt Request (BATTINH = H)
- 199
  Activation Via DCD Interrupt Request (BATTINH = L)
  - 200
    Activation Via Elapsedtime (RTC Alarm) Interrupt Request
- 200
  Activation Via Elapsedtime Interrupt Request (BATTINH = H)
- 200
  Activation Via Elapsedtime Interrupt Request (BATTINH = L)
  - 201
    DRAM Interface Control
    - 201
      Entering Hibernate Mode (EDO DRAM)
    - 202
      Entering Hibernate Mode (SDRAM)
    - 203
      Exiting Hibernate Mode (EDO DRAM)
    - 204
      Exiting Hibernate Mode (SDRAM)
    - 205
      Entering Suspend Mode (EDO DRAM)
    - 206
      Entering Suspend Mode (SDRAM)
    - 207
      Exiting Suspend Mode (EDO DRAM)
    - 207
      Exiting Suspend Mode (SDRAM)
  - 208
    Register Set
    - 209
      PMUINTREG (0X0B00 00A0)
    - 211
      PMUCNTREG (0X0B00 00A2)
    - 213
      PMUWAITREG (0X0B00 00A8)
    - 214
      PMUDIVREG (0X0B00 00AC)
    - 215
      DRAMHIBCTL (0X0B00 00B2)
216
Chapter 11 Realtime Clock Unit (Rtc)
- 216
  General
- 216
  Register Set
  - 217
    Elapsedtime Registers
  - 219
    Elapsedtime Compare Registers
  - 221
    Rtclong1 Registers
  - 223
    Rtclong1 Count Registers
  - 225
    Rtclong2 Registers
  - 227
    Rtclong2 Count Registers
  - 229
    RTC Interrupt Register
230
Chapter 12 Deadman's Switch Unit (Dsu)
- 230
  General
- 230
  Register Set
  - 231
    DSUCNTREG (0X0B00 00E0)
  - 232
    DSUSETREG (0X0B00 00E2)
  - 233
    DSUCLRREG (0X0B00 00E4)
  - 234
    DSUTIMREG (0X0B00 00E6)
- 235
  Register Setting Flow
236
Chapter 13 General Purpose I/O Unit (Giu)
- 236
  Overview
  - 236
    GPIO Pins and Alternate Functions
  - 238
    I/O Direction Control
  - 238
    General-Purpose Registers
- 238
  Alternate Functions Overview
  - 238
    Clocked Serial Interface (CSI)
  - 239
    Serial Interface Channels 1 and 2
  - 241
    LCD Interface
  - 242
    Programmable Chip Selects
  - 242
    16-Bit Bus Cycles
  - 242
    General Purpose Input/Output
  - 243
    Interrupt Requests and Wake-Up Events
- 243
  GPIO(15:0) Interrupt Request Detecting Logic
  - 244
    Register Set
    - 246
      GPMD0REG (0X0B00 0300)
    - 248
      GPMD1REG (0X0B00 0302)
    - 250
      GPMD2REG (0X0B00 0304)
    - 252
      GPMD3REG (0X0B00 0306)
    - 254
      GPDATHREG (0X0B00 0308)
    - 255
      GPDATLREG (0X0B00 030A)
    - 256
      GPINTEN (0X0B00 030C)
    - 257
      GPINTMSK (0X0B00 030E)
    - 258
      GPINTTYPH (0X0B00 0310)
    - 260
      GPINTTYPL (0X0B00 0312)
    - 262
      GPINTSTAT (0X0B00 0314)
    - 263
      GPHIBSTH (0X0B00 0316)
    - 264
      GPHIBSTL (0X0B00 0318)
    - 265
      GPSICTL (0X0B00 031A)
    - 267
      KEYEN (0X0B00 031C)
    - 268
      PCS0STRA (0X0B00 0320)
    - 268
      PCS0STPA (0X0B00 0322)
    - 269
      PCS0HIA (0X0B00 0324)
    - 270
      PCS1STRA (0X0B00 0326)
    - 270
      PCS1STPA (0X0B00 0328)
    - 271
      PCS1HIA (0X0B00 032A)
    - 272
      PCSMODE (0X0B00 032C)
    - 273
      LCDGPMODE (0X0B00 032E)
    - 274
      Miscregn (0X0B00 0330 to 0X0B00 034E)
275
Chapter 14 Touch Panel Interface Unit (Piu)
- 275
  General
  - 276
    Block Diagrams
- 278
  Scan Sequencer State Transition
- 280
  Register Set
  - 281
    PIUCNTREG (0X0B00 0122)
  - 284
    PIUINTREG (0X0B00 0124)
  - 285
    PIUSIVLREG (0X0B00 0126)
  - 286
    PIUSTBLREG (0X0B00 0128)
  - 287
    PIUCMDREG (0X0B00 012A)
  - 289
    PIUASCNREG (0X0B00 0130)
  - 291
    PIUAMSKREG (0X0B00 0132)
  - 292
    PIUCIVLREG (0X0B00 013E)
  - 293
    Piupbnmreg (0X0B00 02A0 to 0X0B00 02AE, 0X0B00 02BC to 0X0B00 02BE)
  - 294
    Piuabnreg (0X0B00 02B0 to 0X0B00 02B6)
- 295
  State Transition Flow
- 297
  Relationships Among TPX, TPY, ADIN, and AUDIOIN Pins and States
- 298
  Timing
  - 298
    Touch/Release Detection Timing
  - 298
    A/D Port Scan Timing
- 299
  Data Loss Conditions
301
Chapter 15 Audio Interface Unit (Aiu)
- 301
  General
- 302
  Register Set
  - 303
    SDMADATREG (0X0B00 0160)
  - 304
    MDMADATREG (0X0B00 0162)
  - 305
    DAVREF_SETUP (0X0B00 0164)
  - 306
    SODATREG (0X0B00 0166)
  - 307
    SCNTREG (0X0B00 0168)
  - 308
    SCNVC_END (0X0B00 016E)
  - 309
    MIDATREG (0X0B00 0170)
  - 310
    MCNTREG (0X0B00 0172)
  - 311
    DVALIDREG (0X0B00 0178)
  - 312
    SEQREG (0X0B00 017A)
  - 313
    INTREG (0X0B00 017C)
  - 314
    MCNVC_END (0X0B00 017E)
- 315
  Operation Sequence
  - 315
    Output (Speaker)
  - 316
    Input (Microphone)
317
Chapter 16 Keyboard Interface Unit (Kiu)
- 317
  General
- 317
  Functional Description
  - 318
    Automatic Keyboard Scan Mode (Auto Scan Mode)
  - 318
    Manual Keyboard Scan Mode (Manual Scan Mode)
  - 318
    Key Press Detection
  - 319
    Scan Operation
  - 320
    Reading Scanned Data
  - 320
    Interrupts and Status Reporting
- 321
  Register Set
  - 322
    Kiudatn (0X0B00 0180 to 0X0B00 018E)
  - 323
    KIUSCANREP (0X0B00 0190)
  - 324
    KIUSCANS (0X0B00 0192)
  - 325
    KIUWKS (0X0B00 0194)
  - 326
    KIUWKI (0X0B00 0196)
  - 327
    KIUINT (0X0B00 0198)
328
Chapter 17 Compactflash Controller (Ecu)
- 328
  General
- 328
  Register Set Summary
- 331
  ECU Control Registers
  - 331
    INTSTATREG (0X0B00 08F8)
  - 332
    INTMSKREG (0X0B00 08FA)
  - 333
    CFG_REG_1 (0X0B00 08FE)
- 334
  ECU Registers
  - 334
    ID_REV_REG (Index: 0X00)
  - 335
    IF_STAT_REG (Index: 0X01)
  - 336
    PWRRSETDRV (Index: 0X02)
  - 337
    ITGENCTREG (Index: 0X03)
  - 338
    CDSTCHGREG (Index: 0X04)
  - 339
    CRDSTATREG (Index: 0X05)
  - 340
    ADWINENREG (Index: 0X06)
  - 341
    IOCTRL_REG (Index: 0X07)
  - 342
    Ioadslbnreg (Index: 0X08, 0X0C)
  - 342
    Ioadshbnreg (Index: 0X09, 0X0D)
  - 343
    Ioslbnreg (Index: 0X0A, 0X0E)
  - 343
    Ioshbnreg (Index: 0X0B, 0X0F)
  - 344
    Sysmemslnreg (Index: 0X10, 0X18, 0X20, 0X28, 0X30)
  - 344
    Memwidn_Reg (Index: 0X11, 0X19, 0X21, 0X29, 0X31)
  - 345
    Sysmemelnreg (Index: 0X12, 0X1A, 0X22, 0X2A, 0X32)
  - 345
    Memseln_Reg (Index: 0X13, 0X1B, 0X23, 0X2B, 0X33)
  - 346
    Memofflnreg (Index: 0X14, 0X1C, 0X24, 0X2C, 0X34)
  - 346
    Memoffhnreg (Index: 0X15, 0X1D, 0X25, 0X2D, 0X35)
  - 347
    DTGENCLREG (Index: 0X16)
  - 348
    GLOCTRLREG (Index: 0X1E)
  - 348
    VOLTSENREG (Index: 0X1F)
  - 349
    VOLTSELREG (Index: 0X2F)
- 350
  Memory Mapping of Compactflash Card
- 352
  Controlling Bus When Compactflash Card Is Used
  - 352
    Controlling Bus Size
  - 352
    Controlling Wait
353
Chapter 18 Led Control Unit (Led)
- 353
  General
- 353
  Register Set
  - 354
    LEDHTSREG (0X0B00 0240)
  - 355
    LEDLTSREG (0X0B00 0242)
  - 356
    LEDCNTREG (0X0B00 0248)
  - 357
    LEDASTCREG (0X0B00 024A)
  - 358
    LEDINTREG (0X0B00 024C)
- 359
  Operation Flow
360
Chapter 19 Serial Interface Unit 1 (Siu1)
- 360
  General
- 360
  Clock Control Logic
- 361
  Register Set
  - 362
    SIURB_1 (0X0C00 0010: LCR7 = 0, Read)
  - 362
    SIUTH_1 (0X0C00 0010: LCR7 = 0, Write)
  - 362
    SIUDLL_1 (0X0C00 0010: LCR7 = 1)
  - 363
    SIUIE_1 (0X0C00 0011: LCR7 = 0)
  - 364
    SIUDLM_1 (0X0C00 0011: LCR7 = 1)
  - 366
    SIUIID_1 (0X0C00 0012: Read)
  - 368
    SIUFC_1 (0X0C00 0012: Write)
  - 371
    SIULC_1 (0X0C00 0013)
  - 372
    SIUMC_1 (0X0C00 0014)
  - 373
    SIULS_1 (0X0C00 0015)
  - 375
    SIUMS_1 (0X0C00 0016)
  - 376
    SIUSC_1 (0X0C00 0017)
  - 376
    SIURESET_1 (0X0C00 0019)
  - 377
    SIUACTMSK_1 (0X0C00 001C)
  - 378
    SIUACTTMR_1 (0X0C00 001E)
379
Chapter 20 Serial Interface Unit 2 (Siu2)
- 379
  General
- 379
  Clock Control Logic
- 380
  Register Set
  - 381
    SIURB_2 (0X0C00 0000: LCR7 = 0, Read)
  - 381
    SIUTH_2 (0X0C00 0000: LCR7 = 0, Write)
  - 381
    SIUDLL_2 (0X0C00 0000: LCR7 = 1)
  - 382
    SIUIE_2 (0X0C00 0001: LCR7 = 0)
  - 383
    SIUDLM_2 (0X0C00 0001: LCR7 = 1)
  - 385
    SIUIID_2 (0X0C00 0002: Read)
  - 387
    SIUFC_2 (0X0C00 0002: Write)
  - 390
    SIULC_2 (0X0C00 0003)
  - 391
    SIUMC_2 (0X0C00 0004)
  - 392
    SIULS_2 (0X0C00 0005)
  - 394
    SIUMS_2 (0X0C00 0006)
  - 395
    SIUSC_2 (0X0C00 0007)
  - 395
    SIUIRSEL_2 (0X0C00 0008)
  - 396
    SIURESET_2 (0X0C00 0009)
  - 396
    SIUCSEL_2 (0X0C00 000A)
  - 397
    SIUACTMSK_2 (0X0C00 000C)
  - 398
    SIUACTTMR_2 (0X0C00 000E)
399
Chapter 21 Lcd Controller
- 399
  Overview
  - 399
    LCD Interface
- 400
  LCD Module Features
- 402
  LCD Controller Specification
  - 402
    Panel Configuration and Interface
  - 405
    Controller Clocks
  - 406
    Palette
  - 406
    Frame Buffer Memory and FIFO
  - 407
    Panel Power ON/OFF Sequence
  - 408
    Operation of LCD Controller
- 413
  Register Set
  - 414
    HRTOTALREG (0X0A00 0400)
  - 414
    HRVISIBREG (0X0A00 0402)
  - 415
    LDCLKSTREG (0X0A00 0404)
  - 415
    LDCLKENDREG (0X0A00 0406)
  - 416
    VRTOTALREG (0X0A00 0408)
  - 416
    VRVISIBREG (0X0A00 040A)
  - 417
    FVSTARTREG (0X0A00 040C)
  - 417
    FVENDREG (0X0A00 040E)
  - 418
    LCDCTRLREG (0X0A00 0410)
  - 419
    LCDINRQREG (0X0A00 0412)
  - 420
    LCDCFGREG0 (0X0A00 0414)
  - 421
    LCDCFGREG1 (0X0A00 0416)
  - 422
    FBSTADREG1 (0X0A00 0418)
  - 422
    FBSTADREG2 (0X0A00 041A)
  - 423
    FBENDADREG1 (0X0A00 0420)
  - 423
    FBENDADREG2 (0X0A00 0422)
  - 424
    FHSTARTREG (0X0A00 0424)
  - 424
    FHENDREG (0X0A00 0426)
  - 425
    PWRCONREG1 (0X0A00 0430)
  - 426
    PWRCONREG2 (0X0A00 0432)
  - 427
    LCDIMSKREG (0X0A00 0434)
  - 428
    CPINDCTREG (0X0A00 047E)
  - 429
    CPALDATREG (0X0A0 0480)
430
Chapter 22 Pll Passive Components
431
Chapter 23 Coprocessor 0 Hazards
436
Appendix A Restrictions On V
- 436
  RSTSW# During Haltimer Operation
- 437
  RSTSW# in Hibernate Mode
439
Appendix B Index

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NEC VR4181 mPD30181 Manuals

Manuals and User Guides for NEC VR4181 mPD30181. We have 1 NEC VR4181 mPD30181 manual available for free PDF download: User Manual

NEC VR4181 mPD30181 User Manual (444 pages)

Table of Contents

29 Chapter 1 Introduction

50 Chapter 2 Pin Functions

67 Chapter 3 Cp0 Registers

91 Chapter 4 Memory Management System

96 Chapter 5 Initialization Interface

108 Chapter 6 Bus Control

142 Chapter 7 Dma Control Unit (Dcu)

156 Chapter 8 Clocked Serial Interface Unit (Csi)

171 Chapter 9 Interrupt Control Unit (Icu)

188 Chapter 10 Power Management Unit (Pmu)

216 Chapter 11 Realtime Clock Unit (Rtc)

230 Chapter 12 Deadman's Switch Unit (Dsu)

236 Chapter 13 General Purpose I/O Unit (Giu)

275 Chapter 14 Touch Panel Interface Unit (Piu)

301 Chapter 15 Audio Interface Unit (Aiu)

317 Chapter 16 Keyboard Interface Unit (Kiu)

328 Chapter 17 Compactflash Controller (Ecu)

353 Chapter 18 Led Control Unit (Led)

360 Chapter 19 Serial Interface Unit 1 (Siu1)

379 Chapter 20 Serial Interface Unit 2 (Siu2)

399 Chapter 21 Lcd Controller

430 Chapter 22 Pll Passive Components

431 Chapter 23 Coprocessor 0 Hazards

436 Appendix A Restrictions On V

439 Appendix B Index

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29
Chapter 1 Introduction

50
Chapter 2 Pin Functions

67
Chapter 3 Cp0 Registers

91
Chapter 4 Memory Management System

96
Chapter 5 Initialization Interface

108
Chapter 6 Bus Control

142
Chapter 7 Dma Control Unit (Dcu)

156
Chapter 8 Clocked Serial Interface Unit (Csi)

171
Chapter 9 Interrupt Control Unit (Icu)

188
Chapter 10 Power Management Unit (Pmu)

216
Chapter 11 Realtime Clock Unit (Rtc)

230
Chapter 12 Deadman's Switch Unit (Dsu)

236
Chapter 13 General Purpose I/O Unit (Giu)

275
Chapter 14 Touch Panel Interface Unit (Piu)

301
Chapter 15 Audio Interface Unit (Aiu)

317
Chapter 16 Keyboard Interface Unit (Kiu)

328
Chapter 17 Compactflash Controller (Ecu)

353
Chapter 18 Led Control Unit (Led)

360
Chapter 19 Serial Interface Unit 1 (Siu1)

379
Chapter 20 Serial Interface Unit 2 (Siu2)

399
Chapter 21 Lcd Controller

430
Chapter 22 Pll Passive Components

431
Chapter 23 Coprocessor 0 Hazards

436
Appendix A Restrictions On V

439
Appendix B Index