NEC VR4181 mPD30181 User Manual page 411

LOCLK
(Output)
FLM
(Output)
SHCLK
(Output)
FPD(7:0)
(Output)
The polarity of the FLM is programmable through the FLMPOL bit. In this diagram the first edge is a rising edge.
The two FLM edges are on the same row in this diagram, but they need not be.
The active edge of the LOCLK is programmable through the LPPOL bit. In this diagram, the first edge is a rising
edge (the falling edge is the active edge).
The polarity of the SHCLK is programmable through the SCLKPOL bit. In this diagram, the first edge is a rising
edge (the falling edge is the active edge).
FLM
(Output)
The definitions of parameters shown in the figures are given in the table below.
CHAPTER 21 LCD CONTROLLER
Figure 21-9. LCD Timing Parameters
T6
T7
T8
T9
T1
T2
0 1
T3 T4
Figure 21-10. FLM Period
User's Manual U14272EJ3V0UM
T5
Invalid
... W−2, W−1
T10
0
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