NEC VR4181 mPD30181 User Manual page 51

64-/32-bit microprocessor hardware
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Pin Identification
ADD(21:0) :
Address Bus
ADIN(2:0) :
Analog Data Input
AUDIOIN :
Audio Input
AUDIOOUT :
Audio Output
BATTINH :
Battery Inhibit
BATTINT# :
Battery Interrupt
CAS# :
Column Address Strobe
CD1#, CD2# :
Card Detect for CompactFlash
CF_AEN# :
Address Enable for CompactFlash Buffer
CF_BUSY# :
Ready/Busy/Interrupt Request for CompactFlash
CF_CE(2:1)# :
Card Enable for CompactFlash
CF_DEN# :
Data Enable for CompactFlash Buffer
CF_DIR :
Data Direction for CompactFlash Buffer
CF_IOIS16# :
I/O is 16 bits for CompactFlash
CF_IOR# :
I/O Read Strobe for CompactFlash
CF_IOW# :
I/O Write Strobe for CompactFlash
CF_OE# :
Output Enable for CompactFlash
CF_REG# :
Register Memory Access for CompactFlash
CF_RESET :
Reset for CompactFlash
CF_STSCHG# : Status Change of CompactFlash
CF_VCCEN# :
V
Enable for CompactFlash
CC
CF_WAIT# :
Wait Input for CompactFlash
CF_WE# :
Write Enable for CompactFlash
CLKEN :
Clock Enable for SDRAM
CLKSEL(2:0) :
Clock Select
CLKX1, CLKX2 : Clock Input
CTS1#, CTS2# : Clear to Send
DATA(15:0) :
Data Bus
DCD1#, DCD2# : Data Carrier Detect
DSR1#, DSR2# : Data Set Ready
DTR1#, DTR2# : Data Terminal Ready
FLM :
First Line Clock for LCD
FPD(7:0) :
Screen Data of LCD
FRM :
Clocked Serial Frame
GND_AD :
Ground for A/D and D/A Converter
GND_IO :
Ground for I/O
GND_LOGIC :
Ground for Logic
GND_OSC :
Ground for Oscillator
GND_PLL :
Ground for PLL
GND_TP :
Ground for Touch Panel
GPIO(31:0) :
General Purpose I/O
IOCS16# :
I/O 16-bit Bus Sizing
IORD# :
I/O Read
IORDY :
I/O Ready
IOWR# :
I/O Write
IRDIN :
IrDA Data Input
IRDOUT :
IrDA Data Output
LCAS# :
Lower Column Address Strobe
LCDCS# :
Chip Select for LCD
Remark # indicates active low.
CHAPTER 2 PIN FUNCTIONS
LDQM :
LEDOUT :
LOCLK :
M :
MEMCS16# :
MEMRD# :
MEMWR# :
MIPS16EN :
MPOWER :
PCS(1:0)# :
POWER :
POWERON :
RAS(1:0)# :
RESET# :
ROMCS(3:0)# :
RSTSW# :
RTCRST# :
RTCX1, RTCX2 : Real-time Clock Input
RTS1#, RTS2# : Request to Send
RxD1, RxD2 :
SCANIN(7:0) :
SCANOUT(7:0) : Scan Data Output
SCK :
SDCLK :
SDCS(1:0)# :
SDRAS# :
SHCLK :
SI :
SO :
SYSCLK :
SYSDIR :
SYSEN# :
TPX(1:0) :
TPY(1:0) :
TxD1, TxD2 :
UBE# :
UCAS# :
UDQM :
VDD_AD :
VDD_IO :
VDD_LOGIC :
VDD_OSC :
VDD_PLL :
VDD_TP :
VPBIAS :
VPGPIO(1:0) :
VPLCD :
User's Manual U14272EJ3V0UM
Lower Byte Enable for SDRAM
LED Output
Load Clock for LCD
LCD Modulation Clock
Memory 16-bit Bus Sizing
Memory Read
Memory Write
MIPS16 Enable
Main Power
Programmable Chip Select
Power Switch
Power On State
Row Address Strobe for DRAM
Reset Output
Chip Select for ROM
Reset Switch
Real-time Clock Reset
Receive Data
Scan Data Input
CSI (Clocked Serial Interface) Clock
Operation Clock for SDRAM
Chip Select for SDRAM
Row Address Strobe for SDRAM
Shift Clock for LCD
Clocked Serial Data Input
Clocked Serial Data Output
System Clock for System Bus
System Data Direction
System Data Enable
Touch Panel Data of X
Touch Panel Data of Y
Transmit Data
Upper Byte Enable for System Bus
Upper Column Address Strobe for DRAM
Upper Byte Enable for SDRAM
Power Supply for A/D and D/A Converter
Power Supply for I/O
Power Supply for Logic
Power Supply for Oscillator
Power Supply for PLL
Power Supply for Touch Panel
Bias Power Control for LCD
General Purpose Output for LCD Panel Power
Control
Logic Power Control for LCD
51

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