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Bit
Name
3, 2
Reserved
1, 0
SCLKDIV(1:0)
This register is used to set the external ISA configurations.
SYSCLK is an operation clock for the external ISA bus, and is output only when an external ISA cycle is
generated.
CHAPTER 6 BUS CONTROL
0 is returned when read
SYSCLK (external ISA bus clock) divisor rate selection
00 : PCLK / 2
01 : PCLK / 3
10 : PCLK / 6
11 : PCLK / 8
User's Manual U14272EJ3V0UM
Function
(2/2)
141
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