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Enables 64-bit addressing in Kernel mode (0 → 32-bit, 1 → 64-bit). 64-bit operations are always
KX:
valid in Kernel mode.
Enables 64-bit addressing and operation in Supervisor mode (0 → 32-bit, 1 → 64-bit).
SX:
Enables 64-bit addressing and operation in User mode (0 → 32-bit, 1 → 64-bit).
UX:
Sets and indicates the operating mode (10 → User, 01 → Supervisor, 00 → Kernel).
KSU:
Sets and indicates the error level (0 → Normal, 1 → Error).
ERL:
Sets and indicates the exception level (0 → Normal, 1 → Exception).
EXL:
Sets and indicates interrupt enabling/disabling (0 → Disabled, 1 → Enabled).
IE:
0:
Reserved for future use. Write 0 in a write operation. When this bit is read, 0 is read.
Figure 3-13 shows the details of the Diagnostic Status (DS) field. All DS field bits other than the TS bit are
writable.
24
Specifies the base address of a TLB Refill exception vector and common exception vector (0 →
BEV:
Normal, 1 → Bootstrap).
Occurs the TLB to be shut down (read-only) (0 → Not shut down, 1 → Shut down). This bit is used
TS:
to avoid any problems that may occur when multiple TLB entries match the same virtual address.
After the TLB has been shut down, reset the processor to enable restart. Note that the TLB is shut
down even if a TLB entry matching a virtual address is marked as being invalid (with the V bit
cleared).
Occurs a Soft Reset or NMI exception (0 → Not occurred, 1 → Occurred).
SR:
CP0 condition bit (0 → False, 1 → True). This bit can be read and written by software only; it
CH:
cannot be accessed by hardware.
CE, DE:
These are prepared to maintain compatibility with the V
hardware.
0:
Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
The Status register has the following fields where the modes and access statuses are set.
CHAPTER 3 CP0 REGISTERS
Figure 3-12. Status Register (2/2)
Figure 3-13. Status Register Diagnostic Status Field
23
22
21
0
BEV
TS
User's Manual U14272EJ3V0UM
20
19
18
17
SR
0
CH
CE
4100, and are not used in the V
R
16
DE
4181
R
77
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