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3.2 REGISTERS
3.2.1 Program Counter (PC)
This 16-bit binary counter holds the address of the program to be executed next (see Fig. 3-6).
Usually, the address is automatically incremented according to the number of bytes of the instruction to be
fetched. If an instruction causing a branch is executed, the contents of the register or immediate data are set.
When RESET is input, the contents at address 00000H of the internal ROM (external memory for the µ PD78213)
are specified in the low-order eight bits of the PC and the contents at address 00001H are specified in the high-order
eight bits of the PC.
15
PC
PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
3.2.2 Program Status Word (PSW)
This 8-bit register consists of flags that are set or reset according to the execution results of an instruction (see Fig.
3-7).
The contents can be read and written in units of eight bits. Each flag can be manipulated by a bit manipulation
instruction. The PSW is saved to a stack when a vectored interrupt request is acknowledged or when the BRK or
PUSH PSW instruction is executed. The PSW is restored when an RETI, RETB, or POP PSW instruction is executed.
When RESET is input, the PSW is set to 02H. (In this state, no interrupt requests can be acknowledged.)
(1) Carry flag (CY)
This flag indicates whether an overflow or underflow occurs when an add/subtract instruction is executed.
If a shift/rotate instruction is executed, the flag holds a shift-out value. If a bit arithmetic/logical instruction
is executed, the flag functions as a bit accumulator.
(2) Interrupt priority status flag (ISP)
This flag manages the priority of maskable vectored interrupts that can currently be acknowledged. If a
maskable interrupt is acknowledged, the contents of the priority designation flag of the acknowledged
interrupt are transferred to the ISP flag. If a non-maskable interrupt (NMI) is acknowledged, this flag is set to
0.
If the ISP flag is set to 0, vectored interrupts assigned a lower priority by the priority designation flag register
(PR0) cannot be acknowledged. If the ISP flag is set to 1, interrupts can be acknowledged, independent of the
priority. The actual acknowledgment of interrupts is controlled according to the status of the IE flag.
The contents are updated each time a maskable vectored interrupt is acknowledged.
For details, see Chapter 12.
Fig. 3-6 Configuration of the Program Counter
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13
12
11
10
9
Fig. 3-7 Configuration of the Program Status Word
7
6
5
PSW
IE
Z
RBS1 AC RBS0
8
7
6
5
4
3
4
3
2
1
0
0
ISP
CY
Chapter 3 CPU Function
2
1
0
3
45
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