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Table 10-1 shows power mode overview and transaction:
Mode
Fullspeed
On
Standby
On
Suspend
On
Hibernate
On
Off
Off
(1) Fullspeed mode
All internal clocks and bus clocks operate. The V
(2) Standby mode
The pipeline clock (PClock) of the CPU core is fixed to high level. PLL, timer/interrupt function of the CPU core,
interrupt clock (MasterOut), internal bus clock (TClock and PCLK), and RTC clock continue their operation.
Therefore, all the on-chip peripheral units continue their operation (operation of the LCD controller and DMA also
continue). The contents of caches and registers in the CPU core are retained.
To enter to Standby mode from Fullspeed mode, execute the STANDBY instruction. After the STANDBY
instruction has passed the WB stage, the V
clocks are shut down, and pipeline operation stops.
To restore to Fullspeed mode, generate an interrupt request of any kind. When the processor restores to
Fullspeed mode from Standby mode, it starts a program execution from the General exception vector (0xBFC0
0380 when BEV = 0 or 0x8000 0180 when BEV = 1).
(3) Suspend mode
The pipeline clock (PClock) of the CPU core and the internal bus clocks (TClock and PCLK) are fixed to high
level. PLL, timer/interrupt function of the CPU core, interrupt clock (MasterOut), and RTC clock continue their
operation.
The contents of caches and registers in the CPU core are retained. The contents of connected DRAMs can be
preserved by putting DRAMs into self-refresh mode.
To enter to Suspend mode from Fullspeed mode, execute a Suspend mode sequence (see 10.6
Interface Control) first. After the SUSPEND instruction has passed the WB stage and DRAMs enter self-refresh
mode, the V
4181 waits until SysAD bus (internal) enters idle state. Then, internal clocks are shut down, and
R
pipeline operation stops.
To restore to Fullspeed mode from Suspend mode, one of the interrupt requests listed in Figure 10-1 (interrupt
requests that can be used are limited since the internal bus clocks (TClock and PCLK) stop). When the
processor restores to Fullspeed mode from Suspend mode, it starts a program execution from the General
exception vector (0xBFC0 0380 when BEV = 0 or 0x8000 0180 when BEV = 1).
190
CHAPTER 10 POWER MANAGEMENT UNIT (PMU)
Table 10-1. Overview of Power Modes
Internal peripheral unit
RTC
ICU
On
On
On
On
On
Off
Off
Off
Off
Off
4181 can perform every function during the Fullspeed mode.
R
4181 waits until SysAD bus (internal) enters idle state. Then, internal
R
User's Manual U14272EJ3V0UM
DMA
LCDC
On
Selectable
On
Selectable
Off
Off
Off
Off
Off
Off
CPU core
Others
On
Off
Off
Off
Off
DRAM
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